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authorEvan Cheng <evan.cheng@apple.com>2007-02-27 21:06:57 +0000
committerEvan Cheng <evan.cheng@apple.com>2007-02-27 21:06:57 +0000
commit659ba970e3d64465cfa1abc4d7d3f9595b5b0878 (patch)
tree2a70217f654bf7e0dbaeb3b7a463388524002863
parent87d266e5930b13fbca8e1e85e9dd5a44b63e2c52 (diff)
Pass IsImp, IsKill, and IsDead to ChangeToRegister.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34688 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--include/llvm/CodeGen/MachineInstr.h9
1 files changed, 5 insertions, 4 deletions
diff --git a/include/llvm/CodeGen/MachineInstr.h b/include/llvm/CodeGen/MachineInstr.h
index ef06d97ea9..3351aa8021 100644
--- a/include/llvm/CodeGen/MachineInstr.h
+++ b/include/llvm/CodeGen/MachineInstr.h
@@ -280,13 +280,14 @@ public:
/// ChangeToRegister - Replace this operand with a new register operand of
/// the specified value. If an operand is known to be an register already,
/// the setReg method should be used.
- void ChangeToRegister(unsigned Reg, bool isDef) {
+ void ChangeToRegister(unsigned Reg, bool isDef, bool isImp = false,
+ bool isKill = false, bool isDead = false) {
opType = MO_Register;
contents.RegNo = Reg;
IsDef = isDef;
- IsImp = false;
- IsKill = false;
- IsDead = false;
+ IsImp = isImp;
+ IsKill = isKill;
+ IsDead = isDead;
}
friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop) {