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authorEvan Cheng <evan.cheng@apple.com>2007-03-13 23:25:11 +0000
committerEvan Cheng <evan.cheng@apple.com>2007-03-13 23:25:11 +0000
commit61230d18d21a5dca1378e994f43934e4b314e595 (patch)
tree18a7736d2d6b2a3ef6b393b6d362d734261d5ac8
parenta13fd108f2c77adc60045859f1df4923b59a9d10 (diff)
Try schedule def + use closer whne Sethi-Ullman numbers are the same.
e.g. t1 = op t2, c1 t3 = op t4, c2 and the following instructions are both ready. t2 = op c3 t4 = op c4 Then schedule t2 = op first. i.e. t4 = op c4 t2 = op c3 t1 = op t2, c1 t3 = op t4, c2 This creates more short live intervals which work better with the register allocator. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35089 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp44
1 files changed, 38 insertions, 6 deletions
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index 66edfbce4e..67fae9b491 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -576,6 +576,15 @@ namespace {
};
}
+static unsigned closestSucc(const SUnit *SU) {
+ unsigned MaxCycle = 0;
+ for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
+ I != E; ++I)
+ if (I->first->Cycle > MaxCycle)
+ MaxCycle = I->first->Cycle;
+ return MaxCycle;
+}
+
// Bottom up
bool bu_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const {
bool LIsTarget = left->Node->isTargetOpcode();
@@ -596,15 +605,38 @@ bool bu_ls_rr_sort::operator()(const SUnit *left, const SUnit *right) const {
unsigned RPriority = SPQ->getNodePriority(right);
if (LPriority > RPriority)
return true;
- else if (LPriority == RPriority)
- if (left->Height > right->Height)
+ else if (LPriority == RPriority) {
+ // Try schedule def + use closer whne Sethi-Ullman numbers are the same.
+ // e.g.
+ // t1 = op t2, c1
+ // t3 = op t4, c2
+ //
+ // and the following instructions are both ready.
+ // t2 = op c3
+ // t4 = op c4
+ //
+ // Then schedule t2 = op first.
+ // i.e.
+ // t4 = op c4
+ // t2 = op c3
+ // t1 = op t2, c1
+ // t3 = op t4, c2
+ //
+ // This creates more short live intervals.
+ unsigned LDist = closestSucc(left);
+ unsigned RDist = closestSucc(right);
+ if (LDist < RDist)
return true;
- else if (left->Height == right->Height)
- if (left->Depth < right->Depth)
+ else if (LDist == RDist)
+ if (left->Height > right->Height)
return true;
- else if (left->Depth == right->Depth)
- if (left->CycleBound > right->CycleBound)
+ else if (left->Height == right->Height)
+ if (left->Depth < right->Depth)
return true;
+ else if (left->Depth == right->Depth)
+ if (left->CycleBound > right->CycleBound)
+ return true;
+ }
return false;
}