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| author | Evan Cheng <evan.cheng@apple.com> | 2007-01-29 22:23:02 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2007-01-29 22:23:02 +0000 |
| commit | 24f7fb3267e358bb589e1856d7c9cc43db5f91d5 (patch) | |
| tree | ab37f8496f766316772fc57b8d245fe6469f7478 | |
| parent | 78268b943669cd0c0e1e874e2a329fcf200bd59b (diff) | |
Comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33633 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMRegisterInfo.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMRegisterInfo.td b/lib/Target/ARM/ARMRegisterInfo.td index 0dfd790b56..445fb26fc0 100644 --- a/lib/Target/ARM/ARMRegisterInfo.td +++ b/lib/Target/ARM/ARMRegisterInfo.td @@ -97,7 +97,7 @@ def GPR : RegisterClass<"ARM", [i32], 32, [R0, R1, R2, R3, R4, R5, R6, }]; // FIXME: We are reserving r12 in case the PEI needs to use it to // generate large stack offset. Make it available once we have register - // scavenging. + // scavenging. Similarly r3 is reserved in Thumb mode for now. let MethodBodies = [{ // FP is R11, R9 is available. static const unsigned ARM_GPR_AO_1[] = { |