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| author | Rafael Espindola <rafael.espindola@gmail.com> | 2006-10-16 17:57:20 +0000 |
|---|---|---|
| committer | Rafael Espindola <rafael.espindola@gmail.com> | 2006-10-16 17:57:20 +0000 |
| commit | 15a6c3e97629c61c8407b57289be53de9237b554 (patch) | |
| tree | 311b41201566dbed2e67e315c1024a03afa7f709 | |
| parent | bb1e2fbc68f91a8df61eeca3a0ff2024b622e2a2 (diff) | |
define the IntBinOp class and use it to implement the multiply instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30978 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 25 |
1 files changed, 13 insertions, 12 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index e5db101865..956f16bf78 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -36,9 +36,8 @@ def iaddr : ComplexPattern<iPTR, 2, "SelectAddrRegImm", [frameindex], []>; //def raddr : ComplexPattern<iPTR, 2, "SelectAddrRegReg", [], []>; //===----------------------------------------------------------------------===// -// Instructions +// Instruction Class Templates //===----------------------------------------------------------------------===// - class InstARM<dag ops, string asmstr, list<dag> pattern> : Instruction { let Namespace = "ARM"; @@ -47,6 +46,15 @@ class InstARM<dag ops, string asmstr, list<dag> pattern> : Instruction { let Pattern = pattern; } +class IntBinOp<string OpcStr, SDNode OpNode> : + InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b), + !strconcat(OpcStr, " $dst, $a, $b"), + [(set IntRegs:$dst, (OpNode IntRegs:$a, IntRegs:$b))]>; + +//===----------------------------------------------------------------------===// +// Instructions +//===----------------------------------------------------------------------===// + def brtarget : Operand<OtherVT>; // Operand for printing out a condition code. @@ -186,18 +194,11 @@ let isTwoAddress = 1 in { IntRegs:$false, imm:$cc))]>; } -def MUL : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b), - "mul $dst, $a, $b", - [(set IntRegs:$dst, (mul IntRegs:$a, IntRegs:$b))]>; +def MUL : IntBinOp<"mul", mul>; let Defs = [R0] in { - def SMULL : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b), - "smull r12, $dst, $a, $b", - [(set IntRegs:$dst, (mulhs IntRegs:$a, IntRegs:$b))]>; - - def UMULL : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b), - "umull r12, $dst, $a, $b", - [(set IntRegs:$dst, (mulhu IntRegs:$a, IntRegs:$b))]>; + def SMULL : IntBinOp<"smull r12,", mulhs>; + def UMULL : IntBinOp<"umull r12,", mulhu>; } def bcond : InstARM<(ops brtarget:$dst, CCOp:$cc), |