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| author | Chris Lattner <sabre@nondot.org> | 2006-05-16 04:20:24 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2006-05-16 04:20:24 +0000 |
| commit | 00402c7ec3aaf4d6a22c1eb97b9e1c1bb3136f46 (patch) | |
| tree | 215e5a889bcba5d29976e4bba2216177b573b295 | |
| parent | 1c8f0536b3a19c0ff9f5a8ba039a771c4bb2bfbc (diff) | |
Fit in 80 cols
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28311 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/PowerPC/PPCISelLowering.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index bc02c9a124..c1d4f403e6 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -1307,7 +1307,7 @@ static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS, unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1); enum { - OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3> + OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3> OP_VMRGHW, OP_VMRGLW, OP_VSPLTISW0, @@ -1978,9 +1978,9 @@ PPCTargetLowering::LowerCallTo(SDOperand Chain, // free GPRs, then we can pass both halves of the i64 in registers. if (GPR_remaining > 0) { SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, - Args[i].first, DAG.getConstant(1, MVT::i32)); + Args[i].first, DAG.getConstant(1, MVT::i32)); SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, - Args[i].first, DAG.getConstant(0, MVT::i32)); + Args[i].first, DAG.getConstant(0, MVT::i32)); args_to_use.push_back(Hi); --GPR_remaining; if (GPR_remaining > 0) { |