diff options
| author | Andrew Lenharth <andrewl@lenharth.org> | 2005-01-26 02:53:56 +0000 |
|---|---|---|
| committer | Andrew Lenharth <andrewl@lenharth.org> | 2005-01-26 02:53:56 +0000 |
| commit | fc16691925f550fcb17c8f03858ea11c488bdf12 (patch) | |
| tree | 198584dc22195354c7097d5b3272bb6d10d9fdfe | |
| parent | 0298118cbbe61c1850db0a09b4d289819c7cf187 (diff) | |
hum, writing on one machine, testing on another...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19844 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/Alpha/AlphaISelPattern.cpp | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp index 5fa16d0e69..c5220bc901 100644 --- a/lib/Target/Alpha/AlphaISelPattern.cpp +++ b/lib/Target/Alpha/AlphaISelPattern.cpp @@ -665,10 +665,11 @@ unsigned ISel::SelectExpr(SDOperand N) { // the ops are expanded into special library calls with // special calling conventions switch(N.getOpcode()) { - case UREM: Opc = Alpha::REMQU; break; - case SREM: Opc = Alpha::REMQ; break; - case UDIV: Opc = Alpha::DIVQU; break; - case SDIV: Opc = Alpha::DIVQ; break; + case ISD::UREM: Opc = Alpha::REMQU; break; + case ISD::SREM: Opc = Alpha::REMQ; break; + case ISD::UDIV: Opc = Alpha::DIVQU; break; + case ISD::SDIV: Opc = Alpha::DIVQ; break; + }; Tmp1 = SelectExpr(N.getOperand(0)); Tmp2 = SelectExpr(N.getOperand(1)); BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2); |