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| author | Chris Lattner <sabre@nondot.org> | 2005-11-19 07:01:30 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2005-11-19 07:01:30 +0000 |
| commit | 6adaf79ad7fd5f3b411e7ff326785891ee47e491 (patch) | |
| tree | debeb678e5fbb623df9ac8efd9d7a4bc7dd65c95 | |
| parent | be7a2ff2dd53a779542039a77fc1524d26ec1224 (diff) | |
Teach the x86 backend about the register constraints of its addressing mode.
Patch by Evan Cheng
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24423 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/Target/X86/X86InstrInfo.td | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index 1bb2fecbb8..40b2481ab4 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -17,8 +17,9 @@ // class X86MemOperand<ValueType Ty> : Operand<Ty> { - let NumMIOperands = 4; let PrintMethod = "printMemoryOperand"; + let NumMIOperands = 4; + let MIOperandInfo = (ops R32, i8imm, R32, i32imm); } def SSECC : Operand<i8> { let PrintMethod = "printSSECC"; |