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authorMisha Brukman <brukman+llvm@gmail.com>2002-11-22 22:40:52 +0000
committerMisha Brukman <brukman+llvm@gmail.com>2002-11-22 22:40:52 +0000
commit35880f394fd547b9bec1e92e92ac68db9a931a58 (patch)
treec02889cd48c16bf9e1e6b8710c6b1b7fd794fb98
parent7b8ba17761180d272d7fa0c1c7371e5b0b9b3872 (diff)
Instead of checking op.getType() against MO_VirtualRegister and
MO_MachineRegister, we no longer distinguish Virtual vs. Machine registers externally, they're ALL registers, all equal. Registers are only differentiated whether they are >= MRegisterInfo::FirstVirtual or not. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4823 91177308-0d34-0410-b5e6-96231b3b80d8
-rw-r--r--include/llvm/CodeGen/MachineInstr.h14
1 files changed, 14 insertions, 0 deletions
diff --git a/include/llvm/CodeGen/MachineInstr.h b/include/llvm/CodeGen/MachineInstr.h
index 833a4a13e6..f3aea0c679 100644
--- a/include/llvm/CodeGen/MachineInstr.h
+++ b/include/llvm/CodeGen/MachineInstr.h
@@ -10,6 +10,7 @@
#define LLVM_CODEGEN_MACHINEINSTR_H
#include "llvm/Annotation.h"
+#include "llvm/Target/MRegisterInfo.h"
#include "Support/iterator"
#include "Support/NonCopyable.h"
#include <vector>
@@ -152,6 +153,19 @@ public:
//
MachineOperandType getType() const { return opType; }
+
+ // This is to finally stop caring whether we have a virtual or machine
+ // register -- an easier interface is to simply call both virtual and machine
+ // registers essentially the same, yet be able to distinguish when
+ // necessary. Thus the instruction selector can just add registers without
+ // abandon, and the register allocator won't be confused.
+ bool isVirtualRegister() const {
+ return (opType == MO_VirtualRegister || opType == MO_MachineRegister)
+ && regNum >= MRegisterInfo::FirstVirtualRegister;
+ }
+
+ bool isMachineRegister() const { return !isVirtualRegister(); }
+
inline Value* getVRegValue () const {
assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
opType == MO_PCRelativeDisp);