llvm/utils/TableGen, branch release_30 http://llvm.org https://git.amat.us/llvm/atom/utils/TableGen?h=release_30 2011-10-14T07:06:56Z Add X86 ANDN instruction. Including instruction selection. 2011-10-14T07:06:56Z Craig Topper craig.topper@gmail.com 2011-10-14T07:06:56Z urn:sha1:54a11176f6a5e07e243f1d87ba19ac3f4681976b git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141947 91177308-0d34-0410-b5e6-96231b3b80d8 Ban rematerializable instructions with side effects. 2011-10-14T01:00:49Z Jakob Stoklund Olesen stoklund@2pi.dk 2011-10-14T01:00:49Z urn:sha1:ccbe603869681aa71b4140e3bf4b4459caf60622 TableGen infers unmodeled side effects on instructions without a pattern. Fix some instruction definitions where that was overlooked. Also raise an error if a rematerializable instruction has unmodeled side effects. That doen't make any sense. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141929 91177308-0d34-0410-b5e6-96231b3b80d8 ARM parsing and encoding for the <option> form of LDC/STC instructions. 2011-10-12T17:34:41Z Jim Grosbach grosbach@apple.com 2011-10-12T17:34:41Z urn:sha1:9b8f2a0b365ea62a5fef80bbaab3cf0252db2fcf git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141786 91177308-0d34-0410-b5e6-96231b3b80d8 Remove extra semicolon. 2011-10-11T19:53:40Z Eli Friedman eli.friedman@gmail.com 2011-10-11T19:53:40Z urn:sha1:830378f6628ad3af1d0293a0b605065532f99e43 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141699 91177308-0d34-0410-b5e6-96231b3b80d8 Fix disassembling of popcntw. Also remove some code that says it accounts for 64BIT_REXW_XD not existing, but it does exist. 2011-10-11T04:34:23Z Craig Topper craig.topper@gmail.com 2011-10-11T04:34:23Z urn:sha1:29480fd798dc6452948f63825ff41c66f09c2493 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141642 91177308-0d34-0410-b5e6-96231b3b80d8 Emit full ED initializers even for pseudo-instructions. 2011-10-10T20:15:49Z Jakob Stoklund Olesen stoklund@2pi.dk 2011-10-10T20:15:49Z urn:sha1:819a2abc72e9e27d105ebc085aac09c6029db4a6 This should unbreak the picky buildbots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141575 91177308-0d34-0410-b5e6-96231b3b80d8 Insert dummy ED table entries for pseudo-instructions. 2011-10-10T18:30:16Z Jakob Stoklund Olesen stoklund@2pi.dk 2011-10-10T18:30:16Z urn:sha1:a0ed0c0fcdd8b94f741f296a67669da3180fb42c The table is indexed by opcode, so simply removing pseudo-instructions creates a wrong mapping from opcode to table entry. Add a test case for xorps which has a very high opcode that exposes this problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141562 91177308-0d34-0410-b5e6-96231b3b80d8 ARM NEON assembly parsing and encoding for VDUP(scalar). 2011-10-07T23:56:00Z Jim Grosbach grosbach@apple.com 2011-10-07T23:56:00Z urn:sha1:460a90540b045c102012da2492999557e6840526 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141446 91177308-0d34-0410-b5e6-96231b3b80d8 Revert part of r141274. Only need to change encoding for xchg %eax, %eax in 64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine. 2011-10-07T05:35:38Z Craig Topper craig.topper@gmail.com 2011-10-07T05:35:38Z urn:sha1:25f6dfd108801d1dc5877c420ef0dd47131aeda7 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141353 91177308-0d34-0410-b5e6-96231b3b80d8 Remove the Clang tblgen backends from LLVM. 2011-10-06T13:21:42Z Peter Collingbourne peter@pcc.me.uk 2011-10-06T13:21:42Z urn:sha1:6d1409dcc517185dca5fe6aef8d0417615951cd3 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141293 91177308-0d34-0410-b5e6-96231b3b80d8