llvm/test/TableGen/MultiClassDefName.td, branch release_31 http://llvm.org https://git.amat.us/llvm/atom/test/TableGen/MultiClassDefName.td?h=release_31 2011-10-06T13:39:59Z s/tblgen/llvm-tblgen/g in a few missed places, including the tests 2011-10-06T13:39:59Z Peter Collingbourne peter@pcc.me.uk 2011-10-06T13:39:59Z urn:sha1:5d5c0624d0f5b9d89a6ad9cbc9fc96b0408ec033 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141294 91177308-0d34-0410-b5e6-96231b3b80d8 Add support for XFAILing valgrind runs with memory leak checking independently 2010-03-20T23:08:45Z Jeffrey Yasskin jyasskin@google.com 2010-03-20T23:08:45Z urn:sha1:32989deb9641cf3878686b5634311a7a125f8f02 of runs without leak checking. We add -vg to the triple for non-checked runs, or -vg_leak for checked runs. Also use this to XFAIL the TableGen tests, since tablegen leaks like a sieve. This includes some valgrindArgs refactoring. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99103 91177308-0d34-0410-b5e6-96231b3b80d8 Allow multiclass def names to contain "#NAME"" where TableGen replaces 2009-05-05T16:28:25Z David Greene greened@obbligato.org 2009-05-05T16:28:25Z urn:sha1:065f259ff5e9e3dcd0da4db3ccd29775c789669d #NAME# with the name of the defm instantiating the multiclass. This is useful for AVX instruction naming where a "V" prefix is standard throughout the ISA. For example: multiclass SSE_AVX_Inst<...> { def SS : Instr<...>; def SD : Instr<...>; def PS : Instr<...>; def PD : Instr<...>; def V#NAME#SS : Instr<...>; def V#NAME#SD : Instr<...>; def V#NAME#PS : Instr<...>; def V#NAME#PD : Instr<...>; } defm ADD : SSE_AVX_Inst<...>; Results in ADDSS ADDSD ADDPS ADDPD VADDSS VADDSD VADDPS VADDPD git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70979 91177308-0d34-0410-b5e6-96231b3b80d8