llvm/test/MC/Disassembler, branch testinghttp://llvm.orghttps://git.amat.us/llvm/atom/test/MC/Disassembler?h=testing2013-03-11T21:17:13ZFixes disassembler crashes on 2013 Haswell RTM instructions.2013-03-11T21:17:13ZKevin Enderbyenderby@apple.com2013-03-11T21:17:13Zurn:sha1:12dccaed9c0368f4f5ef4312c32b375c725c9daf
rdar://13318048
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176828 91177308-0d34-0410-b5e6-96231b3b80d8
AArch64: remove post-encoder method from FCMP (immediate) instructions.2013-02-28T14:46:14ZTim NorthoverTim.Northover@arm.com2013-02-28T14:46:14Zurn:sha1:54a1cf75d2b32cd96ec78f61af5c1bed8d81524d
The work done by the post-encoder (setting architecturally unused bits to 0 as
required) can be done by the existing operand that covers the "#0.0". This
removes at least one use of the discouraged PostEncoderMethod uses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176261 91177308-0d34-0410-b5e6-96231b3b80d8
Make ARMAsmPrinter generate the correct alignment specifier syntax in instructions.2013-02-22T10:01:33ZKristof Beylskristof.beyls@arm.com2013-02-22T10:01:33Zurn:sha1:29e05fe7a885bd03d8570d2bcf14193013776bcd
The Printer will now print instructions with the correct alignment specifier syntax, like
vld1.8 {d16}, [r0:64]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175884 91177308-0d34-0410-b5e6-96231b3b80d8
[XCore] Add missing 2r instructions.2013-02-17T22:38:05ZRichard Osbornerichard@xmos.com2013-02-17T22:38:05Zurn:sha1:8dc741e400213ea8183e09626f0d1f45f14e044f
These instructions are not targeted by the compiler but it is needed for
the MC layer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175407 91177308-0d34-0410-b5e6-96231b3b80d8
[XCore] Add TSETR instruction.2013-02-17T22:32:41ZRichard Osbornerichard@xmos.com2013-02-17T22:32:41Zurn:sha1:763c858edeb76173ee4ef5ab9bf7d750db5d8c4f
This instruction is not targeted by the compiler but it is needed for the
MC layer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175406 91177308-0d34-0410-b5e6-96231b3b80d8
[XCore] Add missing u10 / lu10 instructions.2013-02-17T20:44:48ZRichard Osbornerichard@xmos.com2013-02-17T20:44:48Zurn:sha1:a970dde9060d8994c242bd186bb3636d2caf22d2
These instructions are not targeted by the compiler but they are
needed for the MC layer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175404 91177308-0d34-0410-b5e6-96231b3b80d8
[XCore] Add missing u6 / lu6 instructions.2013-02-17T20:43:17ZRichard Osbornerichard@xmos.com2013-02-17T20:43:17Zurn:sha1:cbe6c88b6811e4641629d111f941879982362fe8
These instructions are not targeted by the compiler but they are
needed for the MC layer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175403 91177308-0d34-0410-b5e6-96231b3b80d8
death to extra whitespace2013-02-14T19:15:14ZKay Tiong Khookkhoo@perfwizard.com2013-02-14T19:15:14Zurn:sha1:951d361c2861602d6c886b62318b60a0befee1ac
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175200 91177308-0d34-0410-b5e6-96231b3b80d8
added basic support for Intel ADX instructions2013-02-14T19:08:21ZKay Tiong Khookkhoo@perfwizard.com2013-02-14T19:08:21Zurn:sha1:7b672ed380cf44894f8b96c52558dcfc136af383
-feature flag, instructions definitions, test cases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175196 91177308-0d34-0410-b5e6-96231b3b80d8
Make ARMAsmParser accept the correct alignment specifier syntax in instructions.2013-02-14T14:46:12ZKristof Beylskristof.beyls@arm.com2013-02-14T14:46:12Zurn:sha1:b1d081230e40e5c86f3cc44a7cfd7241732eabfb
The parser will now accept instructions with alignment specifiers written like
vld1.8 {d16}, [r0:64]
, while also still accepting the incorrect syntax
vld1.8 {d16}, [r0, :64]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175164 91177308-0d34-0410-b5e6-96231b3b80d8