llvm/test/MC/Disassembler/XCore, branch testing http://llvm.org https://git.amat.us/llvm/atom/test/MC/Disassembler/XCore?h=testing 2013-02-17T22:38:05Z [XCore] Add missing 2r instructions. 2013-02-17T22:38:05Z Richard Osborne richard@xmos.com 2013-02-17T22:38:05Z urn:sha1:8dc741e400213ea8183e09626f0d1f45f14e044f These instructions are not targeted by the compiler but it is needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175407 91177308-0d34-0410-b5e6-96231b3b80d8 [XCore] Add TSETR instruction. 2013-02-17T22:32:41Z Richard Osborne richard@xmos.com 2013-02-17T22:32:41Z urn:sha1:763c858edeb76173ee4ef5ab9bf7d750db5d8c4f This instruction is not targeted by the compiler but it is needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175406 91177308-0d34-0410-b5e6-96231b3b80d8 [XCore] Add missing u10 / lu10 instructions. 2013-02-17T20:44:48Z Richard Osborne richard@xmos.com 2013-02-17T20:44:48Z urn:sha1:a970dde9060d8994c242bd186bb3636d2caf22d2 These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175404 91177308-0d34-0410-b5e6-96231b3b80d8 [XCore] Add missing u6 / lu6 instructions. 2013-02-17T20:43:17Z Richard Osborne richard@xmos.com 2013-02-17T20:43:17Z urn:sha1:cbe6c88b6811e4641629d111f941879982362fe8 These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175403 91177308-0d34-0410-b5e6-96231b3b80d8 [XCore] Add missing l2rus instructions. 2013-01-27T22:28:30Z Richard Osborne richard@xmos.com 2013-01-27T22:28:30Z urn:sha1:970a479c02a418726950580e13136acd2a2dc13f These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173634 91177308-0d34-0410-b5e6-96231b3b80d8 [XCore] Add missing l2r instructions. 2013-01-27T21:26:02Z Richard Osborne richard@xmos.com 2013-01-27T21:26:02Z urn:sha1:b719d8b1007f6b31ae6d1a66258a26e6a91749bc These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173629 91177308-0d34-0410-b5e6-96231b3b80d8 [XCore] Add missing 1r instructions. 2013-01-27T20:46:21Z Richard Osborne richard@xmos.com 2013-01-27T20:46:21Z urn:sha1:9d2b1aef1b5bc8926c66b38f03583a77d015e921 These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173624 91177308-0d34-0410-b5e6-96231b3b80d8 [XCore] Add missing 0r instructions. 2013-01-27T20:42:57Z Richard Osborne richard@xmos.com 2013-01-27T20:42:57Z urn:sha1:f5e7e793f196cfba4427321ee9f38ecc8bb8470f These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173623 91177308-0d34-0410-b5e6-96231b3b80d8 Add instruction encodings / disassembly support for l4r instructions. 2013-01-25T21:55:32Z Richard Osborne richard@xmos.com 2013-01-25T21:55:32Z urn:sha1:c47bd9899b639c3384268f871009259c2a94fba4 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173501 91177308-0d34-0410-b5e6-96231b3b80d8 Add instruction encodings / disassembly support for l5r instructions. 2013-01-25T20:20:07Z Richard Osborne richard@xmos.com 2013-01-25T20:20:07Z urn:sha1:3b6a5eefe0ab2199bc69094b390b736ae332b905 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173479 91177308-0d34-0410-b5e6-96231b3b80d8