llvm/test/CodeGen, branch release_32

Merging MIPS GOT changeset into 3.2 release branch.

2012-12-04T19:47:56Z

Merging r168471: Mips direct object xgot support This patch provides support for the MIPS relocations: *) R_MIPS_GOT_HI16 *) R_MIPS_GOT_LO16 *) R_MIPS_CALL_HI16 *) R_MIPS_CALL_LO16 These are used for large GOT instruction sequences. Contributer: Jack Carter Merging r168460: [mips] Generate big GOT code. Merging r168458: [mips] Simplify lowering functions in MipsISelLowering.cpp by using the helper functions added in r168456. Merging r168456: [mips] Add helper functions that create nodes for computing address. Merging r168455: [mips] Add command line option "-mxgot". Merging r168453: [mips] When a node which loads from a GOT is created, pass a MachinePointerInfo referring to a GOT entry. Merging r168450: [mips] Add target operand flag enums for big GOT relocations. Merging r168448: Add relocations used for mips big GOT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_32@169294 91177308-0d34-0410-b5e6-96231b3b80d8

Merging r168837: into the 3.2 release branch.

2012-11-29T02:35:17Z

Avoid rewriting instructions twice. This could cause miscompilations in targets where sub-register composition is not always idempotent (ARM). git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_32@168849 91177308-0d34-0410-b5e6-96231b3b80d8

Merging r167912: into the 3.2 release branch.

2012-11-26T17:01:12Z

Handle DAG CSE adding new uses during ReplaceAllUsesWith. Fixes PR14333. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_32@168596 91177308-0d34-0410-b5e6-96231b3b80d8

Merging r168320: into 3.2 relase branch.

2012-11-23T20:02:28Z

Handle mixed normal and early-clobber defs on inline asm. PR14376. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_32@168527 91177308-0d34-0410-b5e6-96231b3b80d8

Merging r167718 into 3.2 release branch

2012-11-19T22:31:55Z

Fix PR14314 - Fix operand order for atomic sub, where the minuend is the value loaded from memory and the subtrahend is the parameter specified. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_32@168336 91177308-0d34-0410-b5e6-96231b3b80d8

Merging r167948, r168198: into the 3.2 release branch

2012-11-19T22:25:44Z

r168198 [NVPTX] Order global variables in def-use order before emiting them in the final assembly r167948 [NVPTX] Implement custom lowering of loads/stores for i1 Loads from i1 become loads from i8 followed by trunc Stores to i1 become zext to i8 followed by store to i8 git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_32@168335 91177308-0d34-0410-b5e6-96231b3b80d8

Merging r167855 into 3.2 relase branch

2012-11-19T22:17:54Z

Do not consider a machine instruction that uses and defines the same physical register as candidate for common subexpression elimination in MachineCSE. This fixes a bug on PowerPC in MultiSource/Applications/oggenc/oggenc caused by MachineCSE invalidly merging two separate DYNALLOC insns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_32@168334 91177308-0d34-0410-b5e6-96231b3b80d8

[NVPTX] Add more precise PTX/SM target attributes

2012-11-12T03:16:43Z

Each SM and PTX version is modeled as a subtarget feature/CPU. Additionally, PTX 3.1 is added as the default PTX version to be out-of-the-box compatible with CUDA 5.0. Available CPUs for this target: sm_10 - Select the sm_10 processor. sm_11 - Select the sm_11 processor. sm_12 - Select the sm_12 processor. sm_13 - Select the sm_13 processor. sm_20 - Select the sm_20 processor. sm_21 - Select the sm_21 processor. sm_30 - Select the sm_30 processor. sm_35 - Select the sm_35 processor. Available features for this target: ptx30 - Use PTX version 3.0. ptx31 - Use PTX version 3.1. sm_10 - Target SM 1.0. sm_11 - Target SM 1.1. sm_12 - Target SM 1.2. sm_13 - Target SM 1.3. sm_20 - Target SM 2.0. sm_21 - Target SM 2.1. sm_30 - Target SM 3.0. sm_35 - Target SM 3.5. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167699 91177308-0d34-0410-b5e6-96231b3b80d8

Convert an improper CodeGen test to a MC test.

2012-11-10T04:30:40Z

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167663 91177308-0d34-0410-b5e6-96231b3b80d8

xfail a bad test. This is a MC test but it's dependent on a codegen optimization which is now disabled.

2012-11-10T02:34:36Z

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167658 91177308-0d34-0410-b5e6-96231b3b80d8