llvm/test/CodeGen/X86, branch stablehttp://llvm.orghttps://git.amat.us/llvm/atom/test/CodeGen/X86?h=stable2013-04-01T18:12:58ZMerge load/store sequences with adresses: base + index + offset2013-04-01T18:12:58ZArnold Schwaighoferaschwaighofer@apple.com2013-04-01T18:12:58Zurn:sha1:f28a29b776b7dc2b97d09c75d69494f862c216b3
We would also like to merge sequences that involve a variable index like in the
example below.
int index = *idx++
int i0 = c[index+0];
int i1 = c[index+1];
b[0] = i0;
b[1] = i1;
By extending the parsing of the base pointer to handle dags that contain a
base, index, and offset we can handle examples like the one above.
The dag for the code above will look something like:
(load (i64 add (i64 copyfromreg %c)
(i64 signextend (i8 load %index))))
(load (i64 add (i64 copyfromreg %c)
(i64 signextend (i32 add (i32 signextend (i8 load %index))
(i32 1)))))
The code that parses the tree ignores the intermediate sign extensions. However,
if there is a sign extension it needs to be on all indexes.
(load (i64 add (i64 copyfromreg %c)
(i64 signextend (add (i8 load %index)
(i8 1))))
vs
(load (i64 add (i64 copyfromreg %c)
(i64 signextend (i32 add (i32 signextend (i8 load %index))
(i32 1)))))
radar://13536387
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178483 91177308-0d34-0410-b5e6-96231b3b80d8
X86: Promote sitofp <8 x i16> to <8 x i32> when AVX is available.2013-03-31T12:49:15ZBenjamin Kramerbenny.kra@googlemail.com2013-03-31T12:49:15Zurn:sha1:b8f0d89d0584e37e205c04ed5753f57a23365403
A vector sext + sitofp is a lot cheaper than 8 scalar conversions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178448 91177308-0d34-0410-b5e6-96231b3b80d8
DAGCombine: visitXOR can replace a node without returning it, bail out in that case.2013-03-30T21:28:18ZBenjamin Kramerbenny.kra@googlemail.com2013-03-30T21:28:18Zurn:sha1:0b68b758bbb6718fc67423109eeb9df64c711a37
Fixes the crash reported in PR15608.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178429 91177308-0d34-0410-b5e6-96231b3b80d8
Change '@SECREL' suffix to GAS-compatible '@SECREL32'.2013-03-30T16:21:50ZBenjamin Kramerbenny.kra@googlemail.com2013-03-30T16:21:50Zurn:sha1:42734cfb4140287d59d3b35718d62b5f90737499
'@SECREL' is what is used by the Microsoft assembler, but GNU as expects '@SECREL32'.
With the patch, the MC-generated code works fine in combination with a recent GNU as (2.23.51.20120920 here).
Patch by David Nadlinger!
Differential Revision: http://llvm-reviews.chandlerc.com/D429
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178427 91177308-0d34-0410-b5e6-96231b3b80d8
Exclude the X86/complex-fca.ll test at it probably wasn't supposed to work on Windows2013-03-29T21:54:00ZTimur Iskhodzhanovtimurrrr@google.com2013-03-29T21:54:00Zurn:sha1:7d21a64abfd3ad3d8587fa698bc3859acf765502
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178375 91177308-0d34-0410-b5e6-96231b3b80d8
Remove the old CodePlacementOpt pass.2013-03-29T17:14:24ZBenjamin Kramerbenny.kra@googlemail.com2013-03-29T17:14:24Zurn:sha1:74a4533a4290b7c6f1fe04a30ca13ec25c529e0a
It was superseded by MachineBlockPlacement and disabled by default since LLVM 3.1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178349 91177308-0d34-0410-b5e6-96231b3b80d8
Add support of RDSEED defined in AVX2 extension2013-03-28T23:41:26ZMichael Liaomichael.liao@intel.com2013-03-28T23:41:26Zurn:sha1:c26392aa5d9c2dbca2909d6874d181455f8aeb8f
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178314 91177308-0d34-0410-b5e6-96231b3b80d8
Enhance boolean simplification to handle 16-/64-bit RDRAND2013-03-28T23:38:52ZMichael Liaomichael.liao@intel.com2013-03-28T23:38:52Zurn:sha1:258d9b7bc021ebc78f5a3aef3907e225e632edfa
- RDRAND always clears the destination value when a random value is not
available (i.e. CF == 0). This value is truncated or zero-extended as
the false boolean value to be returned. Boolean simplification needs
to skip this 'zext' or 'trunc' node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178312 91177308-0d34-0410-b5e6-96231b3b80d8
Make Win32 put the SRet address into EAX, fixes PR155562013-03-28T21:30:04ZTimur Iskhodzhanovtimurrrr@google.com2013-03-28T21:30:04Zurn:sha1:a46f82dbf94e970f6e61b56a7da8bb19d217f31a
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178291 91177308-0d34-0410-b5e6-96231b3b80d8
Revert "Adding DIImportedModules to DIScopes."2013-03-28T02:44:59ZDavid Blaikiedblaikie@gmail.com2013-03-28T02:44:59Zurn:sha1:72dfb052ab74a9e642256212a50c9b805ce5c943
This reverts commit 342d92c7a0adeabc9ab00f3f0d88d739fe7da4c7.
Turns out we're going with a different schema design to represent
DW_TAG_imported_modules so we won't need this extra field.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178215 91177308-0d34-0410-b5e6-96231b3b80d8