llvm/test/CodeGen/X86, branch release_32 http://llvm.org https://git.amat.us/llvm/atom/test/CodeGen/X86?h=release_32 2012-11-26T17:01:12Z Merging r167912: into the 3.2 release branch. 2012-11-26T17:01:12Z Pawel Wodnicki pawel@32bitmicro.com 2012-11-26T17:01:12Z urn:sha1:3668de5ba6ce154b365ef2f0b001be155c014e6f Handle DAG CSE adding new uses during ReplaceAllUsesWith. Fixes PR14333. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_32@168596 91177308-0d34-0410-b5e6-96231b3b80d8 Merging r168320: into 3.2 relase branch. 2012-11-23T20:02:28Z Pawel Wodnicki pawel@32bitmicro.com 2012-11-23T20:02:28Z urn:sha1:12c349d44181f8083ee9120ddd3b2664c0a1fe8f Handle mixed normal and early-clobber defs on inline asm. PR14376. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_32@168527 91177308-0d34-0410-b5e6-96231b3b80d8 Merging r167718 into 3.2 release branch 2012-11-19T22:31:55Z Pawel Wodnicki pawel@32bitmicro.com 2012-11-19T22:31:55Z urn:sha1:dbf293f3675d5b22560926e1bedd3b99c606e41b Fix PR14314 - Fix operand order for atomic sub, where the minuend is the value loaded from memory and the subtrahend is the parameter specified. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_32@168336 91177308-0d34-0410-b5e6-96231b3b80d8 Cleanup pcmp(e/i)str(m/i) instruction definitions and load folding support. 2012-11-10T01:23:36Z Craig Topper craig.topper@gmail.com 2012-11-10T01:23:36Z urn:sha1:9c7ae01f390b3d7c0fab562e69aba253d28a6dfb git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167652 91177308-0d34-0410-b5e6-96231b3b80d8 Add support of RTM from TSX extension 2012-11-08T07:28:54Z Michael Liao michael.liao@intel.com 2012-11-08T07:28:54Z urn:sha1:be02a90de17f857ba65bbd8a11653ca1bad30adc - Add RTM code generation support throught 3 X86 intrinsics: xbegin()/xend() to start/end a transaction region, and xabort() to abort a tranaction region git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167573 91177308-0d34-0410-b5e6-96231b3b80d8 misched: Heuristics based on the machine model. 2012-11-07T07:05:09Z Andrew Trick atrick@apple.com 2012-11-07T07:05:09Z urn:sha1:3b87f6204fe094610282eea4c8ad7ea4e331d8db misched is disabled by default. With -enable-misched, these heuristics balance the schedule to simultaneously avoid saturating processor resources, expose ILP, and minimize register pressure. I've been analyzing the performance of these heuristics on everything in the llvm test suite in addition to a few other benchmarks. I would like each heuristic check to be verified by a unit test, but I'm still trying to figure out the best way to do that. The heuristics are still in considerable flux, but as they are refined we should be rigorous about unit testing the improvements. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167527 91177308-0d34-0410-b5e6-96231b3b80d8 test/CodeGen/X86/fp-fast.ll: Add +avx. 2012-11-01T02:13:45Z NAKAMURA Takumi geek4civic@gmail.com 2012-11-01T02:13:45Z urn:sha1:b75111f1efa2baf122f07173ab8d16e8d48737b4 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167207 91177308-0d34-0410-b5e6-96231b3b80d8 Add a few more simple fast-math constant propagations and cancellations. 2012-11-01T02:00:53Z Owen Anderson resistor@mac.com 2012-11-01T02:00:53Z urn:sha1:607ebde651f18d68e45724c6e3b3544d4786879f git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167200 91177308-0d34-0410-b5e6-96231b3b80d8 (For X86) Enhancement to add-carray/sub-borrow (adc/sbb) optimization. 2012-10-31T23:11:48Z Shuxin Yang shuxin.llvm@gmail.com 2012-10-31T23:11:48Z urn:sha1:a5526a9bffbd62a14d576f583c206a8a781cc2f1 The adc/sbb optimization is to able to convert following expression into a single adc/sbb instruction: (ult) ... = x + 1 // where the ult is unsigned-less-than comparison (ult) ... = x - 1 This change is to flip the "x >u y" (i.e. ugt comparison) in order to expose the adc/sbb opportunity. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167180 91177308-0d34-0410-b5e6-96231b3b80d8 X86 SSE: update rsqrtss and rcpss to use two source operands and 2012-10-30T23:53:59Z Manman Ren mren@apple.com 2012-10-30T23:53:59Z urn:sha1:dfd0b9b460686ca9491e49dd3647beec5e748a1a the first source operand is tied to the destination operand. This is to accurately model the corresponding instructions where the upper bits are unmodified. rdar://12558838 PR14221 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167064 91177308-0d34-0410-b5e6-96231b3b80d8