llvm/test/CodeGen/Thumb2, branch release_30http://llvm.orghttps://git.amat.us/llvm/atom/test/CodeGen/Thumb2?h=release_302011-09-30T17:41:35ZARM Darwin default relocation model is PIC.2011-09-30T17:41:35ZJim Grosbachgrosbach@apple.com2011-09-30T17:41:35Zurn:sha1:6f09fcf5dae14d68ec9f8731b8c91c04868532e2
This matches clang, so default options in llc and friends are now closer to
clang's defaults.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140863 91177308-0d34-0410-b5e6-96231b3b80d8
Last batch of test conversions to new atomic instructions.2011-09-27T00:17:29ZEli Friedmaneli.friedman@gmail.com2011-09-27T00:17:29Zurn:sha1:139e6699c449f9adea7b54266249715573586f31
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140585 91177308-0d34-0410-b5e6-96231b3b80d8
Convert more tests to new atomic instructions.2011-09-26T21:36:10ZEli Friedmaneli.friedman@gmail.com2011-09-26T21:36:10Zurn:sha1:47d3ee559a4bbac97db38c84e9c89e56eedc6fb9
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140567 91177308-0d34-0410-b5e6-96231b3b80d8
Generalize this test's CHECK statements to handle different indvars modes.2011-09-13T02:46:27ZAndrew Trickatrick@apple.com2011-09-13T02:46:27Zurn:sha1:3c8015aa6c4793a398d1ff0df1752b6d3b41f8e0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139577 91177308-0d34-0410-b5e6-96231b3b80d8
Change ARM / Thumb2 addc / adde and subc / sube modeling to use physical2011-08-30T01:34:54ZEvan Chengevan.cheng@apple.com2011-08-30T01:34:54Zurn:sha1:342e3161d9dd4fa485b47788aa0266f9c91c3832
register dependency (rather than glue them together). This is general
goodness as it gives scheduler more freedom. However it is motivated by
a nasty bug in isel.
When a i64 sub is expanded to subc + sube.
libcall #1
\
\ subc
\ / \
\ / \
\ / libcall #2
sube
If the libcalls are not serialized (i.e. both have chains which are dag
entry), legalizer can serialize them in arbitrary orders. If it's
unlucky, it can force libcall #2 before libcall #1 in the above case.
subc
|
libcall #2
|
libcall #1
|
sube
However since subc and sube are "glued" together, this ends up being a
cycle when the scheduler combine subc and sube as a single scheduling
unit.
The right solution is to fix LegalizeType too chains the libcalls together.
However, LegalizeType is not processing nodes in order so that's harder than
it should be. For now, the move to physical register dependency will do.
rdar://10019576
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138791 91177308-0d34-0410-b5e6-96231b3b80d8
Update tests.2011-08-19T22:19:48ZJim Grosbachgrosbach@apple.com2011-08-19T22:19:48Zurn:sha1:7a32fa1c7825285afb5e570bb9c7a4311e6d6d79
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138116 91177308-0d34-0410-b5e6-96231b3b80d8
Thumb assembly parsing and encoding for LDM instruction.2011-08-18T21:50:53ZJim Grosbachgrosbach@apple.com2011-08-18T21:50:53Zurn:sha1:93b3eff62322803a520e183fdc294bffd6d99bfa
Fix base register type and canonicallize to the "ldm" spelling rather than
"ldmia." Add diagnostics for incorrect writeback token and out-of-range
registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137986 91177308-0d34-0410-b5e6-96231b3b80d8
Fix up the patterns for SXTB, SXTH, UXTB, and UXTH so that they are correctly active without HasT2ExtractPack. PR10611.2011-08-08T19:49:37ZEli Friedmaneli.friedman@gmail.com2011-08-08T19:49:37Zurn:sha1:2cb1dfa4464c8dc551d93e0ce34d7a2f797304db
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137061 91177308-0d34-0410-b5e6-96231b3b80d8
Use MachineBranchProbabilityInfo in If-Conversion instead of its own heuristics.2011-08-03T22:34:43ZJakub Staszakjstaszak@apple.com2011-08-03T22:34:43Zurn:sha1:990f78d53bfe3cf2c82147bc34b457b01e651f25
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136826 91177308-0d34-0410-b5e6-96231b3b80d8
Introduce MCCodeGenInfo, which keeps information that can affect codegen2011-07-19T06:37:02ZEvan Chengevan.cheng@apple.com2011-07-19T06:37:02Zurn:sha1:439661395fd2a2a832dba01c65bc88718528313c
(including compilation, assembly). Move relocation model Reloc::Model from
TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135468 91177308-0d34-0410-b5e6-96231b3b80d8