llvm/test/CodeGen/Thumb2, branch release_28http://llvm.orghttps://git.amat.us/llvm/atom/test/CodeGen/Thumb2?h=release_282010-09-03T18:37:12ZRe-apply r112883:2010-09-03T18:37:12ZJim Grosbachgrosbach@apple.com2010-09-03T18:37:12Zurn:sha1:65482b1bb873dd820f54a24a2f34bd65f2669e5c
"For ARM stack frames that utilize variable sized objects and have either
large local stack areas or require dynamic stack realignment, allocate a
base register via which to access the local frame. This allows efficient
access to frame indices not accessible via the FP (either due to being out
of range or due to dynamic realignment) or the SP (due to variable sized
object allocation). In particular, this greatly improves efficiency of access
to spill slots in Thumb functions which contain VLAs."
r112986 fixed a latent bug exposed by the above.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112989 91177308-0d34-0410-b5e6-96231b3b80d8
Revert "For ARM stack frames that utilize variable sized objects and have either", it is breaking oggenc with Clang for ARMv6.2010-09-03T15:26:42ZDaniel Dunbardaniel@zuster.org2010-09-03T15:26:42Zurn:sha1:6a8700301ca6f8f2f5f787c8d1f5206a7dfceed6
This reverts commit 8d6e29cfda270be483abf638850311670829ee65.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112962 91177308-0d34-0410-b5e6-96231b3b80d8
For ARM stack frames that utilize variable sized objects and have either2010-09-02T22:29:01ZJim Grosbachgrosbach@apple.com2010-09-02T22:29:01Zurn:sha1:1755b3964f931bdd6fa9b4c0138f666ccfa12aca
large local stack areas or require dynamic stack realignment, allocate a
base register via which to access the local frame. This allows efficient
access to frame indices not accessible via the FP (either due to being out
of range or due to dynamic realignment) or the SP (due to variable sized
object allocation). In particular, this greatly improves efficiency of access
to spill slots in Thumb functions which contain VLAs.
rdar://7352504
rdar://8374540
rdar://8355680
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112883 91177308-0d34-0410-b5e6-96231b3b80d8
Now that register allocation properly considers reserved regs, simplify the2010-09-02T18:14:29ZJim Grosbachgrosbach@apple.com2010-09-02T18:14:29Zurn:sha1:e7c14162631d845ff3c465bfe2c6bdf2f59dba70
ARM register class allocation order functions to take advantage of that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112841 91177308-0d34-0410-b5e6-96231b3b80d8
temporarily revert r112664, it is causing a decoding conflict, and 2010-09-01T16:00:50ZChris Lattnersabre@nondot.org2010-09-01T16:00:50Zurn:sha1:5bcb8a6112eca5fb72b39b6b4e608ab1b41e94de
the testcases should be merged.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112711 91177308-0d34-0410-b5e6-96231b3b80d8
We have a chance for an optimization. Consider this code:2010-08-31T22:41:22ZBill Wendlingisanbard@gmail.com2010-08-31T22:41:22Zurn:sha1:43a6c5e2fccadb299c35cb3147d112f706922acd
int x(int t) {
if (t & 256)
return -26;
return 0;
}
We generate this:
tst.w r0, #256
mvn r0, #25
it eq
moveq r0, #0
while gcc generates this:
ands r0, r0, #256
it ne
mvnne r0, #25
bx lr
Scandalous really!
During ISel time, we can look for this particular pattern. One where we have a
"MOVCC" that uses the flag off of a CMPZ that itself is comparing an AND
instruction to 0. Something like this (greatly simplified):
%r0 = ISD::AND ...
ARMISD::CMPZ %r0, 0 @ sets [CPSR]
%r0 = ARMISD::MOVCC 0, -26 @ reads [CPSR]
All we have to do is convert the "ISD::AND" into an "ARM::ANDS" that sets [CPSR]
when it's zero. The zero value will all ready be in the %r0 register and we only
need to change it if the AND wasn't zero. Easy!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112664 91177308-0d34-0410-b5e6-96231b3b80d8
Add alignment arguments to all the NEON load/store intrinsics.2010-08-27T17:13:24ZBob Wilsonbob.wilson@apple.com2010-08-27T17:13:24Zurn:sha1:7a9ef44b3b4ddd2dd9a7f92fc8b46c5e5bed6a81
Update all the tests using those intrinsics and add support for
auto-upgrading bitcode files with the old versions of the intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112271 91177308-0d34-0410-b5e6-96231b3b80d8
ARM/Thumb2: Fix a misselect in getARMCmp, when attempting to adjust a signed2010-08-25T16:58:05ZDaniel Dunbardaniel@zuster.org2010-08-25T16:58:05Zurn:sha1:3cc3283fcbb90924196cc38ee5977b35c4ee28b5
comparison that would overflow.
- The other under/overflow cases can't actually happen because the immediates
which would trigger them are legal (so we don't enter this code), but
adjusted the style to make it clear the transform is always valid.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112053 91177308-0d34-0410-b5e6-96231b3b80d8
Change ARM PKHTB and PKHBT instructions to use a shift_imm operand to avoid2010-08-17T17:23:19ZBob Wilsonbob.wilson@apple.com2010-08-17T17:23:19Zurn:sha1:f955f290c949ff0df7d23cec055efcc4ffeb35d1
printing "lsl #0". This fixes the remaining parts of pr7792. Make
corresponding changes for encoding/decoding these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111251 91177308-0d34-0410-b5e6-96231b3b80d8
Generalize a pattern for PKHTB: an SRL of 16-31 bits will guarantee2010-08-16T22:26:55ZBob Wilsonbob.wilson@apple.com2010-08-16T22:26:55Zurn:sha1:dc66edaced5dacb56f06f52723dd340d5cfe4eab
that the high halfword is zero. The shift need not be exactly 16 bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111196 91177308-0d34-0410-b5e6-96231b3b80d8