llvm/test/CodeGen/SPARC, branch release_30 http://llvm.org https://git.amat.us/llvm/atom/test/CodeGen/SPARC?h=release_30 2011-06-17T07:06:44Z make the asmparser reject function and type redefinitions. 'Merging' hasn't been 2011-06-17T07:06:44Z Chris Lattner sabre@nondot.org 2011-06-17T07:06:44Z urn:sha1:d589099eec8d120b5a7227072c4e717856e2276f needed since llvm-gcc 3.4 days. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133248 91177308-0d34-0410-b5e6-96231b3b80d8 Fix more register and coalescing dependencies. 2011-05-04T19:02:11Z Jakob Stoklund Olesen stoklund@2pi.dk 2011-05-04T19:02:11Z urn:sha1:96169b189ca75e22f297a62a77aaf0dc4832f4a5 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130859 91177308-0d34-0410-b5e6-96231b3b80d8 These tests no longer require linear scan because reserved register coalescing is now universal. 2011-04-05T21:40:41Z Jakob Stoklund Olesen stoklund@2pi.dk 2011-04-05T21:40:41Z urn:sha1:c5ddb740895f4f2efe58bcd6d092d07d0bdb2527 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128936 91177308-0d34-0410-b5e6-96231b3b80d8 Fix Mips, Sparc, and XCore tests that were dependent on register allocation. 2011-03-31T18:42:43Z Jakob Stoklund Olesen stoklund@2pi.dk 2011-03-31T18:42:43Z urn:sha1:a6f74992441c998886bbf26696ea7ec9746df537 Add an extra run with -regalloc=basic to keep them honest. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128654 91177308-0d34-0410-b5e6-96231b3b80d8 Generate correct Sparc32 ABI compliant code for functions that return a struct. 2011-02-21T03:42:44Z Venkatraman Govindaraju venkatra@cs.wisc.edu 2011-02-21T03:42:44Z urn:sha1:58269b973256bf2436cac0f047aa277fe4bc01dd git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126108 91177308-0d34-0410-b5e6-96231b3b80d8 Prevent IMPLICIT_DEF/KILL to become a delay filler instruction in SPARC backend. 2011-02-12T19:02:33Z Venkatraman Govindaraju venkatra@cs.wisc.edu 2011-02-12T19:02:33Z urn:sha1:cc5bd4a56140f8c7381afa686f28b361fd540436 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125444 91177308-0d34-0410-b5e6-96231b3b80d8 Pass sret arguments through the stack instead of through registers in Sparc backend. It makes the code generated more compliant with the sparc32 ABI. 2011-01-22T13:05:16Z Venkatraman Govindaraju venkatra@cs.wisc.edu 2011-01-22T13:05:16Z urn:sha1:8184e289db45acd0bd8bbf7087f7a1274ef55f15 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124030 91177308-0d34-0410-b5e6-96231b3b80d8 Added ICC, FCC as uses of movcc instruction to generate correct code when -mattr=v9 is used. 2011-01-22T11:36:24Z Venkatraman Govindaraju venkatra@cs.wisc.edu 2011-01-22T11:36:24Z urn:sha1:e105a3901fecce76e789566ecbfbc87a5b4ce899 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124027 91177308-0d34-0410-b5e6-96231b3b80d8 Sparc backend: 2011-01-21T22:00:00Z Venkatraman Govindaraju venkatra@cs.wisc.edu 2011-01-21T22:00:00Z urn:sha1:fc3faa75cbadd8a1020941ec85adfda1d2f49688 Rename FLUSH to FLUSHW. Output "ta 3" instead of a "flushw" instruction if v8 instruction set is used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123997 91177308-0d34-0410-b5e6-96231b3b80d8 Implement support for byval arguments in Sparc backend. 2011-01-21T14:00:01Z Venkatraman Govindaraju venkatra@cs.wisc.edu 2011-01-21T14:00:01Z urn:sha1:46713296e0da8f413b94b9c2b82b079e6e3bd6e2 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123974 91177308-0d34-0410-b5e6-96231b3b80d8