llvm/test/CodeGen/NVPTX, branch testing

Propagate DAG node ordering during type legalization and instruction selection

2013-03-20T00:10:32Z

A node's ordering is only propagated during legalization if (a) the new node does not have an ordering (is not a CSE'd node), or (b) the new node has an ordering that is higher than the node being legalized. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177465 91177308-0d34-0410-b5e6-96231b3b80d8

[NVPTX] Disable vector registers

2013-02-12T14:18:49Z

Vectors were being manually scalarized by the backend. Instead, let the target-independent code do all of the work. The manual scalarization was from a time before good target-independent support for scalarization in LLVM. However, this forces us to specially-handle vector loads and stores, which we can turn into PTX instructions that produce/consume multiple operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174968 91177308-0d34-0410-b5e6-96231b3b80d8

[NVPTX] Remove NoCapture from address space conversion intrinsics. NoCapture is not valid in this case, and was causing incorrect optimizations.

2013-02-11T18:56:35Z

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174896 91177308-0d34-0410-b5e6-96231b3b80d8

[NVPTX] Fix crash with unnamed struct arguments

2012-12-05T20:50:28Z

Patch by Eric Holk git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169418 91177308-0d34-0410-b5e6-96231b3b80d8

Teach the legalizer how to handle operands for VSELECT nodes

2012-11-29T14:26:28Z

If we need to split the operand of a VSELECT, it must be the mask operand. We split the entire VSELECT operand with EXTRACT_SUBVECTOR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168883 91177308-0d34-0410-b5e6-96231b3b80d8

Allow targets to prefer TypeSplitVector over TypePromoteInteger when computing the legalization method for vectors

2012-11-29T14:26:24Z

For some targets, it is desirable to prefer scalarizing instead of promoting to a larger legal type, such as . git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168882 91177308-0d34-0410-b5e6-96231b3b80d8

[NVPTX] Order global variables in def-use order before emiting them in the final assembly

2012-11-16T21:03:51Z

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168198 91177308-0d34-0410-b5e6-96231b3b80d8

[NVPTX] Implement custom lowering of loads/stores for i1

2012-11-14T19:19:16Z

Loads from i1 become loads from i8 followed by trunc Stores to i1 become zext to i8 followed by store to i8 Fixes PR13291 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167948 91177308-0d34-0410-b5e6-96231b3b80d8

[NVPTX] Add more precise PTX/SM target attributes

2012-11-12T03:16:43Z

Each SM and PTX version is modeled as a subtarget feature/CPU. Additionally, PTX 3.1 is added as the default PTX version to be out-of-the-box compatible with CUDA 5.0. Available CPUs for this target: sm_10 - Select the sm_10 processor. sm_11 - Select the sm_11 processor. sm_12 - Select the sm_12 processor. sm_13 - Select the sm_13 processor. sm_20 - Select the sm_20 processor. sm_21 - Select the sm_21 processor. sm_30 - Select the sm_30 processor. sm_35 - Select the sm_35 processor. Available features for this target: ptx30 - Use PTX version 3.0. ptx31 - Use PTX version 3.1. sm_10 - Target SM 1.0. sm_11 - Target SM 1.1. sm_12 - Target SM 1.2. sm_13 - Target SM 1.3. sm_20 - Target SM 2.0. sm_21 - Target SM 2.1. sm_30 - Target SM 3.0. sm_35 - Target SM 3.5. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167699 91177308-0d34-0410-b5e6-96231b3b80d8

[NVPTX] Use ABI alignment for parameters when alignment is not specified.

2012-11-09T23:50:24Z

Affects SM 2.0+. Fixes bug 13324. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167646 91177308-0d34-0410-b5e6-96231b3b80d8