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<title>llvm/test/CodeGen/NVPTX, branch release_33</title>
<subtitle>http://llvm.org</subtitle>
<id>https://git.amat.us/llvm/atom/test/CodeGen/NVPTX?h=release_33</id>
<link rel='self' href='https://git.amat.us/llvm/atom/test/CodeGen/NVPTX?h=release_33'/>
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<updated>2013-03-30T14:29:30Z</updated>
<entry>
<title>[NVPTX] Remove support for SM &lt; 2.0.  This was never fully supported anyway.</title>
<updated>2013-03-30T14:29:30Z</updated>
<author>
<name>Justin Holewinski</name>
<email>jholewinski@nvidia.com</email>
</author>
<published>2013-03-30T14:29:30Z</published>
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<id>urn:sha1:b24fc1c7f7545362fe283730d5532fa7e7375c9e</id>
<content type='text'>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178417 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>[NVPTX] Add NVVMReflect pass to allow compile-time selection of</title>
<updated>2013-03-30T14:29:25Z</updated>
<author>
<name>Justin Holewinski</name>
<email>jholewinski@nvidia.com</email>
</author>
<published>2013-03-30T14:29:25Z</published>
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<id>urn:sha1:21fdcb02716f5eae097abfd2f44e40563e90180a</id>
<content type='text'>
specific code paths.

This allows us to write code like:

  if (__nvvm_reflect("FOO"))
    // Do something
  else
    // Do something else

and compile into a library, then give "FOO" a value at kernel
compile-time so the check becomes a no-op.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178416 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>[NVPTX] Fix handling of vector arguments</title>
<updated>2013-03-24T21:17:47Z</updated>
<author>
<name>Justin Holewinski</name>
<email>jholewinski@nvidia.com</email>
</author>
<published>2013-03-24T21:17:47Z</published>
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<id>urn:sha1:1ce53cb526d23a3988fb12a5294ab1fcb2eb840f</id>
<content type='text'>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177847 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Propagate DAG node ordering during type legalization and instruction selection</title>
<updated>2013-03-20T00:10:32Z</updated>
<author>
<name>Justin Holewinski</name>
<email>jholewinski@nvidia.com</email>
</author>
<published>2013-03-20T00:10:32Z</published>
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<id>urn:sha1:d73dc544f5e37e6d58befc71e57da3c132804543</id>
<content type='text'>
A node's ordering is only propagated during legalization if (a) the new node does
not have an ordering (is not a CSE'd node), or (b) the new node has an ordering
that is higher than the node being legalized.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177465 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>[NVPTX] Disable vector registers</title>
<updated>2013-02-12T14:18:49Z</updated>
<author>
<name>Justin Holewinski</name>
<email>jholewinski@nvidia.com</email>
</author>
<published>2013-02-12T14:18:49Z</published>
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<id>urn:sha1:7eacad03efda36e09ebd96e95d7891cadaaa9087</id>
<content type='text'>
Vectors were being manually scalarized by the backend.  Instead,
let the target-independent code do all of the work.  The manual
scalarization was from a time before good target-independent support
for scalarization in LLVM. However, this forces us to specially-handle
vector loads and stores, which we can turn into PTX instructions that
produce/consume multiple operands.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174968 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>[NVPTX] Remove NoCapture from address space conversion intrinsics. NoCapture is not valid in this case, and was causing incorrect optimizations.</title>
<updated>2013-02-11T18:56:35Z</updated>
<author>
<name>Justin Holewinski</name>
<email>jholewinski@nvidia.com</email>
</author>
<published>2013-02-11T18:56:35Z</published>
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<id>urn:sha1:ff5adad9f39f60dc9f1caadef03b6aa7922ed168</id>
<content type='text'>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174896 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>[NVPTX] Fix crash with unnamed struct arguments</title>
<updated>2012-12-05T20:50:28Z</updated>
<author>
<name>Justin Holewinski</name>
<email>jholewinski@nvidia.com</email>
</author>
<published>2012-12-05T20:50:28Z</published>
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<id>urn:sha1:2f1086137dbabad072c98bd4d8dab15525ca4991</id>
<content type='text'>
Patch by Eric Holk

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169418 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Teach the legalizer how to handle operands for VSELECT nodes</title>
<updated>2012-11-29T14:26:28Z</updated>
<author>
<name>Justin Holewinski</name>
<email>jholewinski@nvidia.com</email>
</author>
<published>2012-11-29T14:26:28Z</published>
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<id>urn:sha1:7f128ea00c5358729906a9b98f844e887a1c3d73</id>
<content type='text'>
If we need to split the operand of a VSELECT, it must be the mask operand. We
split the entire VSELECT operand with EXTRACT_SUBVECTOR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168883 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Allow targets to prefer TypeSplitVector over TypePromoteInteger when computing the legalization method for vectors</title>
<updated>2012-11-29T14:26:24Z</updated>
<author>
<name>Justin Holewinski</name>
<email>jholewinski@nvidia.com</email>
</author>
<published>2012-11-29T14:26:24Z</published>
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<id>urn:sha1:3d200255d5b93344c1ab0a5ba4b47a52cfa5893e</id>
<content type='text'>
For some targets, it is desirable to prefer scalarizing &lt;N x i1&gt; instead of promoting to a larger legal type, such as &lt;N x i32&gt;.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168882 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>[NVPTX] Order global variables in def-use order before emiting them in the final assembly</title>
<updated>2012-11-16T21:03:51Z</updated>
<author>
<name>Justin Holewinski</name>
<email>jholewinski@nvidia.com</email>
</author>
<published>2012-11-16T21:03:51Z</published>
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<id>urn:sha1:2085d00d09f4f3678a6c67da46df3a04e31b499c</id>
<content type='text'>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168198 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
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