llvm/test/CodeGen/NVPTX, branch release_32 http://llvm.org https://git.amat.us/llvm/atom/test/CodeGen/NVPTX?h=release_32 2012-11-19T22:25:44Z Merging r167948, r168198: into the 3.2 release branch 2012-11-19T22:25:44Z Pawel Wodnicki pawel@32bitmicro.com 2012-11-19T22:25:44Z urn:sha1:c8a344e16acf6df8d402729da2e1dff7c5187633 r168198 [NVPTX] Order global variables in def-use order before emiting them in the final assembly r167948 [NVPTX] Implement custom lowering of loads/stores for i1 Loads from i1 become loads from i8 followed by trunc Stores to i1 become zext to i8 followed by store to i8 git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_32@168335 91177308-0d34-0410-b5e6-96231b3b80d8 [NVPTX] Add more precise PTX/SM target attributes 2012-11-12T03:16:43Z Justin Holewinski jholewinski@nvidia.com 2012-11-12T03:16:43Z urn:sha1:08e9cb46feb0c8e08e3d309a0f9fd75a04ca54fb Each SM and PTX version is modeled as a subtarget feature/CPU. Additionally, PTX 3.1 is added as the default PTX version to be out-of-the-box compatible with CUDA 5.0. Available CPUs for this target: sm_10 - Select the sm_10 processor. sm_11 - Select the sm_11 processor. sm_12 - Select the sm_12 processor. sm_13 - Select the sm_13 processor. sm_20 - Select the sm_20 processor. sm_21 - Select the sm_21 processor. sm_30 - Select the sm_30 processor. sm_35 - Select the sm_35 processor. Available features for this target: ptx30 - Use PTX version 3.0. ptx31 - Use PTX version 3.1. sm_10 - Target SM 1.0. sm_11 - Target SM 1.1. sm_12 - Target SM 1.2. sm_13 - Target SM 1.3. sm_20 - Target SM 2.0. sm_21 - Target SM 2.1. sm_30 - Target SM 3.0. sm_35 - Target SM 3.5. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167699 91177308-0d34-0410-b5e6-96231b3b80d8 [NVPTX] Use ABI alignment for parameters when alignment is not specified. 2012-11-09T23:50:24Z Justin Holewinski justin.holewinski@gmail.com 2012-11-09T23:50:24Z urn:sha1:89443ff7ae81e6a439b5b67e5dd587a450090599 Affects SM 2.0+. Fixes bug 13324. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167646 91177308-0d34-0410-b5e6-96231b3b80d8 Add llvm.fabs intrinsic. 2012-05-28T21:48:37Z Peter Collingbourne peter@pcc.me.uk 2012-05-28T21:48:37Z urn:sha1:b34d3aa35b199969168f41a12e92e5d2f0e9367f git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157594 91177308-0d34-0410-b5e6-96231b3b80d8 [NVPTX] Add a new test case for the newly-enabled call handling 2012-05-25T17:20:38Z Justin Holewinski jholewinski@nvidia.com 2012-05-25T17:20:38Z urn:sha1:968b09d03f92f2c80ebe2347b6c65ed30bc3279b NV_CONTRIB git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157485 91177308-0d34-0410-b5e6-96231b3b80d8 This patch adds a new NVPTX back-end to LLVM which supports code generation for NVIDIA PTX 3.0. This back-end will (eventually) replace the current PTX back-end, while maintaining compatibility with it. 2012-05-04T20:18:50Z Justin Holewinski jholewinski@nvidia.com 2012-05-04T20:18:50Z urn:sha1:49683f3c961379fbc088871a5d6304950f1f1cbc The new target machines are: nvptx (old ptx32) => 32-bit PTX nvptx64 (old ptx64) => 64-bit PTX The sources are based on the internal NVIDIA NVPTX back-end, and contain more functionality than the current PTX back-end currently provides. NV_CONTRIB git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156196 91177308-0d34-0410-b5e6-96231b3b80d8