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<title>llvm/test/CodeGen/MSP430, branch release_27</title>
<subtitle>http://llvm.org</subtitle>
<id>https://git.amat.us/llvm/atom/test/CodeGen/MSP430?h=release_27</id>
<link rel='self' href='https://git.amat.us/llvm/atom/test/CodeGen/MSP430?h=release_27'/>
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<updated>2010-03-06T11:41:12Z</updated>
<entry>
<title>Do not use '&amp;' prefix for globals when register base field is non-zero, otherwise msp430-as will silently miscompile the code (TI's assembler report an error though).</title>
<updated>2010-03-06T11:41:12Z</updated>
<author>
<name>Anton Korobeynikov</name>
<email>asl@math.spbu.ru</email>
</author>
<published>2010-03-06T11:41:12Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=9aff323a074658eee2de69862d202a8638b59c05'/>
<id>urn:sha1:9aff323a074658eee2de69862d202a8638b59c05</id>
<content type='text'>
This fixes PR6349

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97877 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Fix some issues in WalkChainUsers dealing with </title>
<updated>2010-03-02T22:20:06Z</updated>
<author>
<name>Chris Lattner</name>
<email>sabre@nondot.org</email>
</author>
<published>2010-03-02T22:20:06Z</published>
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<id>urn:sha1:d1b738298359846b9cccaa0931e6ec1fc59a6d87</id>
<content type='text'>
CopyToReg/CopyFromReg/INLINEASM.  These are annoying because
they have the same opcode before an after isel.  Fix this by
setting their NodeID to -1 to indicate that they are selected,
just like what automatically happens when selecting things that
end up being machine nodes.

With that done, give IsLegalToFold a new flag that causes it to
ignore chains.  This lets the HandleMergeInputChains routine be
the one place that validates chains after a match is successful,
enabling the new hotness in chain processing.  This smarter
chain processing eliminates the need for "PreprocessRMW" in the
X86 and MSP430 backends and enables MSP to start matching it's
multiple mem operand instructions more aggressively.

I currently #if out the dead code in the X86 backend and MSP 
backend, I'll remove it for real in a follow-on patch.

The testcase changes are:
  test/CodeGen/X86/sse3.ll: we generate better code
  test/CodeGen/X86/store_op_load_fold2.ll: PreprocessRMW was 
      miscompiling this before, we now generate correct code
      Convert it to filecheck while I'm at it.
  test/CodeGen/MSP430/Inst16mm.ll: Add a testcase for mem/mem
      folding to make anton happy. :)




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97596 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Change the scheduler from adding nodes in allnodes order</title>
<updated>2010-02-24T06:11:37Z</updated>
<author>
<name>Chris Lattner</name>
<email>sabre@nondot.org</email>
</author>
<published>2010-02-24T06:11:37Z</published>
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<id>urn:sha1:736a6ea3a2a5322db0e09d97651a1acc07502e41</id>
<content type='text'>
to adding them in a determinstic order (bottom up from 
the root) based on the structure of the graph itself.

This updates tests for some random changes, interesting
bits: CodeGen/Blackfin/promote-logic.ll no longer crashes.
I have no idea why, but that's good right?

CodeGen/X86/2009-07-16-LoadFoldingBug.ll also fails, but
now compiles to have one fewer constant pool entry, making
the expected load that was being folded disappear.  Since it
is an unreduced mass of gnast, I just removed it.

This fixes PR6370


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97023 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>no need to run llvm-as here.</title>
<updated>2010-02-22T23:34:12Z</updated>
<author>
<name>Chris Lattner</name>
<email>sabre@nondot.org</email>
</author>
<published>2010-02-22T23:34:12Z</published>
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<id>urn:sha1:48eb39b1abe1476f248d8b8e87ca4bb7496ce346</id>
<content type='text'>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96826 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>IT turns out that during jumpless setcc lowering eq and ne were swapped.</title>
<updated>2010-02-21T12:28:58Z</updated>
<author>
<name>Anton Korobeynikov</name>
<email>asl@math.spbu.ru</email>
</author>
<published>2010-02-21T12:28:58Z</published>
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<id>urn:sha1:455080ff100c9383bc2619ae8ad86a02f61c3b00</id>
<content type='text'>
This fixes PR6348

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96734 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Reenable tests</title>
<updated>2010-01-15T21:19:26Z</updated>
<author>
<name>Anton Korobeynikov</name>
<email>asl@math.spbu.ru</email>
</author>
<published>2010-01-15T21:19:26Z</published>
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<id>urn:sha1:12c71a53b54ce2fae68b9d7c5003dab4d6e2b760</id>
<content type='text'>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93555 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Temporary disable tests</title>
<updated>2010-01-15T02:09:27Z</updated>
<author>
<name>Anton Korobeynikov</name>
<email>asl@math.spbu.ru</email>
</author>
<published>2010-01-15T02:09:27Z</published>
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<id>urn:sha1:8396a17bc3a6d2cb9aedd22fc15780ac8ab41662</id>
<content type='text'>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93501 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Add variable-width shifts for MSP430</title>
<updated>2010-01-14T22:09:38Z</updated>
<author>
<name>Anton Korobeynikov</name>
<email>asl@math.spbu.ru</email>
</author>
<published>2010-01-14T22:09:38Z</published>
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<id>urn:sha1:74a265686dd3e816c0f580c77d07fbb9e8bf3ddd</id>
<content type='text'>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93468 91177308-0d34-0410-b5e6-96231b3b80d8
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</entry>
<entry>
<title>Delete useless trailing semicolons.</title>
<updated>2010-01-05T17:55:26Z</updated>
<author>
<name>Dan Gohman</name>
<email>gohman@apple.com</email>
</author>
<published>2010-01-05T17:55:26Z</published>
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<id>urn:sha1:aceba31b7a04fd28680209b2677915378877bc13</id>
<content type='text'>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92740 91177308-0d34-0410-b5e6-96231b3b80d8
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</entry>
<entry>
<title>Use more sensible type for flags in asms.  PR 5570.</title>
<updated>2009-12-23T07:32:51Z</updated>
<author>
<name>Dale Johannesen</name>
<email>dalej@apple.com</email>
</author>
<published>2009-12-23T07:32:51Z</published>
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<id>urn:sha1:9949933d6eb406bc74f7df7a0180a11c050a236f</id>
<content type='text'>
Patch by Sylve`re Teissier (sorry, ASCII only).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91988 91177308-0d34-0410-b5e6-96231b3b80d8
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