llvm/test/CodeGen/Hexagon, branch testing http://llvm.org https://git.amat.us/llvm/atom/test/CodeGen/Hexagon?h=testing 2013-03-14T19:08:03Z Hexagon: Removed asserts regarding alignment and offset. 2013-03-14T19:08:03Z Jyotsna Verma jverma@codeaurora.org 2013-03-14T19:08:03Z urn:sha1:cec50e6da221edeef922a5d5f85081ba66b08dab We are warning the user about the alignment, so we should not assert. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177103 91177308-0d34-0410-b5e6-96231b3b80d8 Hexagon: Add patterns for zero extended loads from i1->i64. 2013-03-08T14:15:15Z Jyotsna Verma jverma@codeaurora.org 2013-03-08T14:15:15Z urn:sha1:86df21767a0465f9044929e9bfc829fb34d99c19 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176689 91177308-0d34-0410-b5e6-96231b3b80d8 Hexagon: Handle i8, i16 and i1 Var Args. 2013-03-07T20:28:34Z Jyotsna Verma jverma@codeaurora.org 2013-03-07T20:28:34Z urn:sha1:a4dd8d67320d86ca7dfd88cb3d0c189cab713a88 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176647 91177308-0d34-0410-b5e6-96231b3b80d8 Hexagon: Add support to lower block address. 2013-03-07T19:10:28Z Jyotsna Verma jverma@codeaurora.org 2013-03-07T19:10:28Z urn:sha1:b6716187ca8cc33817fb7446d9d9bdcb708c3f35 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176637 91177308-0d34-0410-b5e6-96231b3b80d8 reverting patch 176508. 2013-03-05T20:29:23Z Jyotsna Verma jverma@codeaurora.org 2013-03-05T20:29:23Z urn:sha1:0d44328ce89b19602074676378a92c3b36bb0d83 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176513 91177308-0d34-0410-b5e6-96231b3b80d8 Hexagon: Add support for lowering block address. 2013-03-05T19:37:46Z Jyotsna Verma jverma@codeaurora.org 2013-03-05T19:37:46Z urn:sha1:c34f17140fb3bc66ba48af9beb5060d4064b353f git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176508 91177308-0d34-0410-b5e6-96231b3b80d8 Hexagon: Expand addc, adde, subc and sube. 2013-03-05T19:04:47Z Jyotsna Verma jverma@codeaurora.org 2013-03-05T19:04:47Z urn:sha1:18daead3ff41902a61ff3344cfa77ac8aba5586d git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176505 91177308-0d34-0410-b5e6-96231b3b80d8 Hexagon: Add encoding bits to the TFR64 instructions. 2013-03-05T18:42:28Z Jyotsna Verma jverma@codeaurora.org 2013-03-05T18:42:28Z urn:sha1:ee0ef13eba037055d8dc315fc924d967c8f8ce0a Set imMoveImm, isAsCheapAsAMove flags for TFRI instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176499 91177308-0d34-0410-b5e6-96231b3b80d8 Hexagon: Add constant extender support framework. 2013-03-01T17:37:13Z Jyotsna Verma jverma@codeaurora.org 2013-03-01T17:37:13Z urn:sha1:ef94c6c85eed42d16fde51ee4415d27bb281a2ca git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176358 91177308-0d34-0410-b5e6-96231b3b80d8 Hexagon: Expand cttz, ctlz, and ctpop for now. 2013-02-21T19:39:40Z Anshuman Dasgupta adasgupt@codeaurora.org 2013-02-21T19:39:40Z urn:sha1:6585d3b64b04b788faad79ba6cf4e592ebf4658d git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175783 91177308-0d34-0410-b5e6-96231b3b80d8