llvm/test/CodeGen/Hexagon, branch release_33 http://llvm.org https://git.amat.us/llvm/atom/test/CodeGen/Hexagon?h=release_33 2013-05-02T20:22:51Z Hexagon - Add peephole optimizations for zero extends. 2013-05-02T20:22:51Z Pranav Bhandarkar pranavb@codeaurora.org 2013-05-02T20:22:51Z urn:sha1:02d937d86420409210291accd9aa023d97b4a8b5 * lib/Target/Hexagon/HexagonInstrInfo.td: Add patterns to combine a sequence of a pair of i32->i64 extensions followed by a "bitwise or" into COMBINE_rr. * lib/Target/Hexagon/HexagonPeephole.cpp: Copy propagate Rx in the instruction Rp = COMBINE_Ir_V4(0, Rx) to the uses of Rp:subreg_loreg. * test/CodeGen/Hexagon/union-1.ll: New test. * test/CodeGen/Hexagon/combine_ir.ll: Fix test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180946 91177308-0d34-0410-b5e6-96231b3b80d8 TBAA: remove !tbaa from testing cases if not used. 2013-04-30T17:52:57Z Manman Ren mren@apple.com 2013-04-30T17:52:57Z urn:sha1:2dc50d306752c8672d1543feb88517705cdb25e7 This will make it easier to turn on struct-path aware TBAA since the metadata format will change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180796 91177308-0d34-0410-b5e6-96231b3b80d8 Hexagon: Use multiclass for combine and STri[bhwd]_shl_V4 instructions. 2013-04-23T21:17:40Z Jyotsna Verma jverma@codeaurora.org 2013-04-23T21:17:40Z urn:sha1:42ba77db537274c797d74ddfa80902e58901529a git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180145 91177308-0d34-0410-b5e6-96231b3b80d8 Hexagon: Remove assembler mapped instruction definitions. 2013-04-23T19:15:55Z Jyotsna Verma jverma@codeaurora.org 2013-04-23T19:15:55Z urn:sha1:47089c91aea7bdd8b2fa81223dfdd3484a20fd12 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180133 91177308-0d34-0410-b5e6-96231b3b80d8 Hexagon: Remove duplicate instructions to handle global/immediate values 2013-04-23T17:11:46Z Jyotsna Verma jverma@codeaurora.org 2013-04-23T17:11:46Z urn:sha1:3d7b39e7d4d3cef9f859f5965fbf959e251ee3ee for absolute/absolute-set addressing modes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180120 91177308-0d34-0410-b5e6-96231b3b80d8 Hexagon: Enable SupportDebugInfomation and DwarfInSection flags. 2013-03-28T19:34:49Z Jyotsna Verma jverma@codeaurora.org 2013-03-28T19:34:49Z urn:sha1:e41c7d4890c8363f21bee4a2a9414760ff24e473 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178279 91177308-0d34-0410-b5e6-96231b3b80d8 Hexagon: Use multiclass for gp-relative instructions. 2013-03-28T16:25:57Z Jyotsna Verma jverma@codeaurora.org 2013-03-28T16:25:57Z urn:sha1:4f2ef94d6ad77cbdef068e85674d0101d331051e Remove noV4T gp-relative instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178246 91177308-0d34-0410-b5e6-96231b3b80d8 Hexagon: Use multiclass for aslh, asrh, sxtb, sxth, zxtb and zxth. 2013-03-26T15:43:57Z Jyotsna Verma jverma@codeaurora.org 2013-03-26T15:43:57Z urn:sha1:7bb9585c6e2528e3e4e928e7691dd97a106e3de0 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178032 91177308-0d34-0410-b5e6-96231b3b80d8 Hexagon: Add and enable memops setbit, clrbit, &,|,+,- for byte, short, and word. 2013-03-22T18:41:34Z Jyotsna Verma jverma@codeaurora.org 2013-03-22T18:41:34Z urn:sha1:97e602b574b38d57384f0f877700357531a3d23e git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177747 91177308-0d34-0410-b5e6-96231b3b80d8 Hexagon: Removed asserts regarding alignment and offset. 2013-03-14T19:08:03Z Jyotsna Verma jverma@codeaurora.org 2013-03-14T19:08:03Z urn:sha1:cec50e6da221edeef922a5d5f85081ba66b08dab We are warning the user about the alignment, so we should not assert. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177103 91177308-0d34-0410-b5e6-96231b3b80d8