llvm/test/CodeGen/Hexagon, branch master http://llvm.org https://git.amat.us/llvm/atom/test/CodeGen/Hexagon?h=master 2013-05-10T20:27:34Z Hexagon: Fix switch cases in HexagonVLIWPacketizer.cpp. 2013-05-10T20:27:34Z Jyotsna Verma jverma@codeaurora.org 2013-05-10T20:27:34Z urn:sha1:1a35b8e2eb165624013d5a2eaf8b673f026999fc git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181624 91177308-0d34-0410-b5e6-96231b3b80d8 Hexagon: Use relation map for getMatchingCondBranchOpcode() and 2013-05-09T18:25:44Z Jyotsna Verma jverma@codeaurora.org 2013-05-09T18:25:44Z urn:sha1:f4f60b10e4ccd14511f5c83f4e83dbcad6740f63 getInvertedPredicatedOpcode() functions instead of switch cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181530 91177308-0d34-0410-b5e6-96231b3b80d8 Hexagon: Fix Small Data support to handle -G 0 correctly. 2013-05-07T19:53:00Z Jyotsna Verma jverma@codeaurora.org 2013-05-07T19:53:00Z urn:sha1:f931f691ee23d431135481fcf23a58658824ca67 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181344 91177308-0d34-0410-b5e6-96231b3b80d8 Reverting r181331. 2013-05-07T17:12:35Z Jyotsna Verma jverma@codeaurora.org 2013-05-07T17:12:35Z urn:sha1:ddcf3ee768d41f16c6f10c38f7faee440d6b9f55 Missing file, HexagonSplitConst32AndConst64.cpp, from lib/Target/Hexagon/CMakeLists.txt. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181334 91177308-0d34-0410-b5e6-96231b3b80d8 Hexagon: Fix Small Data support to handle -G 0 correctly. 2013-05-07T16:42:15Z Jyotsna Verma jverma@codeaurora.org 2013-05-07T16:42:15Z urn:sha1:81fda3b4d55886ba40093e818125679bec126866 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181331 91177308-0d34-0410-b5e6-96231b3b80d8 Hexagon - Add peephole optimizations for zero extends. 2013-05-02T20:22:51Z Pranav Bhandarkar pranavb@codeaurora.org 2013-05-02T20:22:51Z urn:sha1:02d937d86420409210291accd9aa023d97b4a8b5 * lib/Target/Hexagon/HexagonInstrInfo.td: Add patterns to combine a sequence of a pair of i32->i64 extensions followed by a "bitwise or" into COMBINE_rr. * lib/Target/Hexagon/HexagonPeephole.cpp: Copy propagate Rx in the instruction Rp = COMBINE_Ir_V4(0, Rx) to the uses of Rp:subreg_loreg. * test/CodeGen/Hexagon/union-1.ll: New test. * test/CodeGen/Hexagon/combine_ir.ll: Fix test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180946 91177308-0d34-0410-b5e6-96231b3b80d8 TBAA: remove !tbaa from testing cases if not used. 2013-04-30T17:52:57Z Manman Ren mren@apple.com 2013-04-30T17:52:57Z urn:sha1:2dc50d306752c8672d1543feb88517705cdb25e7 This will make it easier to turn on struct-path aware TBAA since the metadata format will change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180796 91177308-0d34-0410-b5e6-96231b3b80d8 Hexagon: Use multiclass for combine and STri[bhwd]_shl_V4 instructions. 2013-04-23T21:17:40Z Jyotsna Verma jverma@codeaurora.org 2013-04-23T21:17:40Z urn:sha1:42ba77db537274c797d74ddfa80902e58901529a git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180145 91177308-0d34-0410-b5e6-96231b3b80d8 Hexagon: Remove assembler mapped instruction definitions. 2013-04-23T19:15:55Z Jyotsna Verma jverma@codeaurora.org 2013-04-23T19:15:55Z urn:sha1:47089c91aea7bdd8b2fa81223dfdd3484a20fd12 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180133 91177308-0d34-0410-b5e6-96231b3b80d8 Hexagon: Remove duplicate instructions to handle global/immediate values 2013-04-23T17:11:46Z Jyotsna Verma jverma@codeaurora.org 2013-04-23T17:11:46Z urn:sha1:3d7b39e7d4d3cef9f859f5965fbf959e251ee3ee for absolute/absolute-set addressing modes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180120 91177308-0d34-0410-b5e6-96231b3b80d8