llvm/test/CodeGen/CellSPU, branch release_28http://llvm.orghttps://git.amat.us/llvm/atom/test/CodeGen/CellSPU?h=release_282010-08-29T12:41:50ZFix lowering of INSERT_VECTOR_ELT in SPU. 2010-08-29T12:41:50ZKalle Raiskilakalle.raiskila@nokia.com2010-08-29T12:41:50Zurn:sha1:bd887df8b960404f3f1a2f5a6a98ec8c2aa8394d
The IDX was treated as byte index, not element index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112422 91177308-0d34-0410-b5e6-96231b3b80d8
Fix SPU BE to use all the available return registers.2010-08-24T11:50:48ZKalle Raiskilakalle.raiskila@nokia.com2010-08-24T11:50:48Zurn:sha1:55aebef654d11a11e24c8d6680f6647b73a715f7
llc used to assert on the added testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111911 91177308-0d34-0410-b5e6-96231b3b80d8
Fix a bug with insertelement on SPU. 2010-08-18T10:20:29ZKalle Raiskilakalle.raiskila@nokia.com2010-08-18T10:20:29Zurn:sha1:ca9460f5a0e1863dfe873c8e364464fc849524c2
The previous algorithm in LowerVECTOR_SHUFFLE
didn't check all requirements for "monotonic" shuffles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111361 91177308-0d34-0410-b5e6-96231b3b80d8
Remove all traces of v2[i,f]32 on SPU. 2010-08-18T10:04:39ZKalle Raiskilakalle.raiskila@nokia.com2010-08-18T10:04:39Zurn:sha1:86a791284ae473a8820144be77ce92db8bd3028e
The "half vectors" are now widened to full size by the legalizer.
The only exception is in parameter passing, where half vectors are
expanded. This causes changes to some dejagnu tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111360 91177308-0d34-0410-b5e6-96231b3b80d8
Change SPU C calling convention to match that described in 2010-08-18T09:50:30ZKalle Raiskilakalle.raiskila@nokia.com2010-08-18T09:50:30Zurn:sha1:44ff5f5435c60558b47d975655385f15b0dee01c
"SPU Application Binary Interface Specification, v1.9" by
IBM.
Specifically: use r3-r74 to pass parameters and the return value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111358 91177308-0d34-0410-b5e6-96231b3b80d8
Have SPU handle halfvec stores aligned by 8 bytes.2010-08-09T16:33:00ZKalle Raiskilakalle.raiskila@nokia.com2010-08-09T16:33:00Zurn:sha1:99534bb81a0d945edd61d4db17549bde8449f94c
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110576 91177308-0d34-0410-b5e6-96231b3b80d8
Make SPU backend handle insertelement and 2010-08-04T13:59:48ZKalle Raiskilakalle.raiskila@nokia.com2010-08-04T13:59:48Zurn:sha1:bc2697cca0fc58434b6177923d46612267781825
store for "half vectors"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110198 91177308-0d34-0410-b5e6-96231b3b80d8
More SPU v2f32 stuff added: insertelement and shuffle.2010-08-02T11:22:10ZKalle Raiskilakalle.raiskila@nokia.com2010-08-02T11:22:10Zurn:sha1:e1c9159f63c60b4d64e80b7912eedf43b93b12e0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110038 91177308-0d34-0410-b5e6-96231b3b80d8
Add preliminary v2f32 support for SPU. Like with v2i32, we just2010-08-02T10:25:47ZKalle Raiskilakalle.raiskila@nokia.com2010-08-02T10:25:47Zurn:sha1:c9fda996fc1cafc7d6c705b9d560e46e83df2ecf
duplicate the instructions and operate on half vectors.
Also reorder code in SPUInstrInfo.td for better coherency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110037 91177308-0d34-0410-b5e6-96231b3b80d8
Add preliminary v2i32 support for SPU backend. As there are no2010-08-02T08:54:39ZKalle Raiskilakalle.raiskila@nokia.com2010-08-02T08:54:39Zurn:sha1:82fe467ca59094c19c500038f0a282b70daa1d00
such registers in SPU, this support boils down to "emulating"
them by duplicating instructions on the general purpose registers.
This adds the most basic operations on v2i32: passing parameters,
addition, subtraction, multiplication and a few others.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110035 91177308-0d34-0410-b5e6-96231b3b80d8