llvm/test/CodeGen/CellSPU, branch release_25

Used "-enable-unsafe-fp-math" to allow this transformation - (a * b -c) = c - a *b.

2009-01-31T06:50:54Z

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63475 91177308-0d34-0410-b5e6-96231b3b80d8

CellSPU:

2009-01-26T03:31:40Z

- Rename fcmp.ll test to fcmp32.ll, start adding new double tests to fcmp64.ll - Fix select_bits.ll test - Capitulate to the DAGCombiner and move i64 constant loads to instruction selection (SPUISelDAGtoDAG.cpp). DAGCombiner will insert all kinds of 64-bit optimizations after operation legalization occurs and now we have to do most of the work that instruction selection should be doing twice (once to determine if v2i64 build_vector can be handled by SelectCode(), which then runs all of the predicates a second time to select the necessary instructions.) But, CellSPU is a good citizen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62990 91177308-0d34-0410-b5e6-96231b3b80d8

Don't rely on grep -w working.

2009-01-21T09:41:42Z

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62682 91177308-0d34-0410-b5e6-96231b3b80d8

CellSPU:

2009-01-21T04:58:48Z

- Ensure that (operation) legalization emits proper FDIV libcall when needed. - Fix various bugs encountered during llvm-spu-gcc build, along with various cleanups. - Start supporting double precision comparisons for remaining libgcc2 build. Discovered interesting DAGCombiner feature, which is currently solved via custom lowering (64-bit constants are not legal on CellSPU, but DAGCombiner insists on inserting one anyway.) - Update README. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62664 91177308-0d34-0410-b5e6-96231b3b80d8

Add the private linkage.

2009-01-15T20:18:42Z

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62279 91177308-0d34-0410-b5e6-96231b3b80d8

- Convert remaining i64 custom lowering into custom instruction emission

2009-01-15T04:41:47Z

sequences in SPUDAGToDAGISel.cpp and SPU64InstrInfo.td, killing custom DAG node types as needed. - i64 mul is now a legal instruction, but emits an instruction sequence that stretches tblgen and the imagination, as well as violating laws of several small countries and most southern US states (just kidding, but looking at a function with 80+ parameters is really weird and just plain wrong.) - Update tests as needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62254 91177308-0d34-0410-b5e6-96231b3b80d8

Fix off-by-one error in traversing an array; this fixes a test.

2009-01-07T23:07:29Z

The error was reported by gcc-4.3.0 during compilation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61896 91177308-0d34-0410-b5e6-96231b3b80d8

CellSPU:

2009-01-06T03:36:14Z

- Fix bugs 3194, 3195: i128 load/stores produce correct code (although, we need to ensure that i128 is 16-byte aligned in real life), and 128 zero- extends are supported. - New td file: SPU128InstrInfo.td: this is where all new i128 support should be put in the future. - Continue to hammer on i64 operations and test cases; ensure that the only remaining problem will be i64 mul. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61784 91177308-0d34-0410-b5e6-96231b3b80d8

CellSPU:

2009-01-05T04:05:53Z

- Teach SPU64InstrInfo.td about the remaining signed comparisons, update tests accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61672 91177308-0d34-0410-b5e6-96231b3b80d8

CellSPU:

2009-01-05T01:35:22Z

- Add an 8-bit operation test, which doesn't do much at this point. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61665 91177308-0d34-0410-b5e6-96231b3b80d8