llvm/test/CodeGen/CellSPU, branch release_24 http://llvm.org https://git.amat.us/llvm/atom/test/CodeGen/CellSPU?h=release_24 2008-08-31T02:59:23Z Revert the "XFAIL" for the rotate_ops.ll testcase. Instead, mark ISD::ROTR 2008-08-31T02:59:23Z Bill Wendling isanbard@gmail.com 2008-08-31T02:59:23Z urn:sha1:9440e35b9875757e5556a01f585aa6b2dd9a0c48 instructions in CellSPU as "Expand" so that they won't be generated. I added a "FIXME" so that this hack can be addressed and reverted once ISD::ROTR is supported in the .td files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55582 91177308-0d34-0410-b5e6-96231b3b80d8 CellSPU doesn't appear to support fully the "ISD::ROTR" operation. The DAG 2008-08-31T02:32:12Z Bill Wendling isanbard@gmail.com 2008-08-31T02:32:12Z urn:sha1:70fcb6bf58268798b9b3ee7983eb9c9e1aed4811 combiner can now generate ROTR if the backend says that it can handle it. Cell SPU says this, but gets an error from code gen saying that it can't select ROTR. I'm xfailing this test until this can be fixed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55579 91177308-0d34-0410-b5e6-96231b3b80d8 Add necessary 64-bit support so that gcc frontend compiles (mostly). Current 2008-06-02T22:18:03Z Scott Michel scottm@aero.org 2008-06-02T22:18:03Z urn:sha1:8bf61e8c2a39bcf070c39848fea83eda57851ebb issue is operand promotion for setcc/select... but looks like the fundamental stuff is implemented for CellSPU. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51884 91177308-0d34-0410-b5e6-96231b3b80d8 sabre brings to my attention that the 'tr' suffix is also obsolete 2008-05-20T21:00:03Z Gabor Greif ggreif@gmail.com 2008-05-20T21:00:03Z urn:sha1:f6cadc440cbf04330b3cda9a3c76728f08035203 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51349 91177308-0d34-0410-b5e6-96231b3b80d8 Rename the last test with .llx extension to .ll, resolve duplicate test by renaming to isnan2. Now that no test has llx ending there is no need to search for them from dg.exp too. 2008-05-20T19:52:04Z Gabor Greif ggreif@gmail.com 2008-05-20T19:52:04Z urn:sha1:722243bd402aaed698a279cb323cf37554befd53 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51328 91177308-0d34-0410-b5e6-96231b3b80d8 Update and_ops.ll according to the recent dagcombiner changes. 2008-04-28T23:26:22Z Dan Gohman gohman@apple.com 2008-04-28T23:26:22Z urn:sha1:1d7153976c04723127bf6269b33a8ba81ae874d5 Add a new test, and_ops_more.ll, which is XFAIL'd, to record the parts of and_ops.ll that were affected by this change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50379 91177308-0d34-0410-b5e6-96231b3b80d8 Upgrade these tests for the current intrinsic prototypes. 2008-04-14T18:19:18Z Dan Gohman gohman@apple.com 2008-04-14T18:19:18Z urn:sha1:63f7ba085f2ce561663656dcc81ef81ae9654358 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49669 91177308-0d34-0410-b5e6-96231b3b80d8 Add more patterns to match in the integer comparison test harnesses. 2008-03-20T00:51:36Z Scott Michel scottm@aero.org 2008-03-20T00:51:36Z urn:sha1:79698f60c4693ba305ba994b8349a3f6a6d6031e Fix bugs encountered, mostly due to range matching for immediates; the CellSPU's 10-bit immediates are sign extended, covering a larger range of unsigned values. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48575 91177308-0d34-0410-b5e6-96231b3b80d8 - Style cleanup in IA64ISelLowering.h: add 'virtual' keyword for consistency. 2008-03-10T23:49:09Z Scott Michel scottm@aero.org 2008-03-10T23:49:09Z urn:sha1:405fba12ce4874e0b599b19168b1d29d1c64ffab - Add test pattern matching in CellSPU's icmp32.ll test harness - Fix CellSPU fcmp.ll-generated assert. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48197 91177308-0d34-0410-b5e6-96231b3b80d8 Integer comparison tests for CellSPU. 2008-03-10T16:58:52Z Scott Michel scottm@aero.org 2008-03-10T16:58:52Z urn:sha1:78c47fa50b903d5dcb4e07a5c048a35cbc2add9e git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48152 91177308-0d34-0410-b5e6-96231b3b80d8