llvm/test/CodeGen/ARM, branch release_32

Merging r168837: into the 3.2 release branch.

2012-11-29T02:35:17Z

Avoid rewriting instructions twice. This could cause miscompilations in targets where sub-register composition is not always idempotent (ARM). git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_32@168849 91177308-0d34-0410-b5e6-96231b3b80d8

Disable the Thumb no-return call optimization:

2012-11-10T02:09:05Z

mov lr, pc b.w _foo The "mov" instruction doesn't set bit zero to one, it's putting incorrect value in lr. It messes up backtraces. rdar://12663632 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167657 91177308-0d34-0410-b5e6-96231b3b80d8

Recommit modified r167540.

2012-11-08T09:51:45Z

Improve ARM build attribute emission for architectures types. This also changes the default architecture emitted for a generic CPU to "v7". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167574 91177308-0d34-0410-b5e6-96231b3b80d8

Vext Lowering was missing opportunities

2012-11-02T21:32:17Z

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167318 91177308-0d34-0410-b5e6-96231b3b80d8

Change ForceSizeOpt attribute into MinSize attribute

2012-10-30T16:32:52Z

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167020 91177308-0d34-0410-b5e6-96231b3b80d8

Completely disallow partial copies in adjustCopiesBackFrom().

2012-10-29T17:51:52Z

Partial copies can show up even when CoalescerPair.isPartial() returns false. For example: %vreg24:dsub_0 = COPY %vreg31:dsub_0; QPR:%vreg24,%vreg31 Such a partial-partial copy is not good enough for the transformation adjustCopiesBackFrom() needs to do. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166944 91177308-0d34-0410-b5e6-96231b3b80d8

[code size][ARM] Emit regular call instructions instead of the move, branch sequence

2012-10-27T01:10:17Z

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166854 91177308-0d34-0410-b5e6-96231b3b80d8

Revert r163298 "Optimize codegen for VSETLNi{8,16,32} operating on Q registers."

2012-10-26T23:39:46Z

Keep the integer_insertelement test case, the new coalescer can handle this kind of lane insertion without help from pseudo-instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166835 91177308-0d34-0410-b5e6-96231b3b80d8

Fix a miscompilation caused by a typo. When turning a adde with negative value

2012-10-24T19:53:01Z

into a sbc with a positive number, the immediate should be complemented, not negated. Also added a missing pattern for ARM codegen. rdar://12559385 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166613 91177308-0d34-0410-b5e6-96231b3b80d8

When a block ends in an indirect branch, add its successors to the machine basic block.

2012-10-22T23:30:04Z

The CFG of the machine function needs to know that the targets of the indirect branch are successors to the indirect branch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166448 91177308-0d34-0410-b5e6-96231b3b80d8