llvm/test/CodeGen/ARM, branch release_28http://llvm.orghttps://git.amat.us/llvm/atom/test/CodeGen/ARM?h=release_282010-09-10T10:21:50ZApproved by Evan.2010-09-10T10:21:50ZBill Wendlingisanbard@gmail.com2010-09-10T10:21:50Zurn:sha1:3c941a5acb0c466307af6c585339ab588e290395
$ svn merge -c 113576 https://llvm.org/svn/llvm-project/llvm/trunk
--- Merging r113576 into '.':
U test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll
U lib/Target/ARM/ARMLoadStoreOptimizer.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_28@113583 91177308-0d34-0410-b5e6-96231b3b80d8
Replace NEON vabdl, vaba, and vabal intrinsics with combinations of the2010-09-03T01:35:08ZBob Wilsonbob.wilson@apple.com2010-09-03T01:35:08Zurn:sha1:eb0c3d372906df9c61a31651a0ba278034447e94
vabd intrinsic and add and/or zext operations. In the case of vaba, this
also avoids the need for a DAG combine pattern to combine vabd with add.
Update tests. Auto-upgrade the old intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112941 91177308-0d34-0410-b5e6-96231b3b80d8
Fix an unnecessary XFAIL2010-09-02T20:19:24ZSandeep Pateldeeppatel1987@gmail.com2010-09-02T20:19:24Zurn:sha1:b7a11b5399b29db57ec817e2972fe06f5a4dfb78
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112853 91177308-0d34-0410-b5e6-96231b3b80d8
Now that register allocation properly considers reserved regs, simplify the2010-09-02T18:14:29ZJim Grosbachgrosbach@apple.com2010-09-02T18:14:29Zurn:sha1:e7c14162631d845ff3c465bfe2c6bdf2f59dba70
ARM register class allocation order functions to take advantage of that.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112841 91177308-0d34-0410-b5e6-96231b3b80d8
Convert VLD1 and VLD2 instructions to use pseudo-instructions until2010-09-02T16:00:54ZBob Wilsonbob.wilson@apple.com2010-09-02T16:00:54Zurn:sha1:ffde080ae615906545eb33dab30e7bc47c2ac838
after regalloc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112825 91177308-0d34-0410-b5e6-96231b3b80d8
Remove NEON vmull, vmlal, and vmlsl intrinsics, replacing them with multiply,2010-09-01T23:50:19ZBob Wilsonbob.wilson@apple.com2010-09-01T23:50:19Zurn:sha1:d0b69cf1198dadbb7bdfc385334b67f60f756539
add, and subtract operations with zero-extended or sign-extended vectors.
Update tests. Add auto-upgrade support for the old intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112773 91177308-0d34-0410-b5e6-96231b3b80d8
temporarily revert r112664, it is causing a decoding conflict, and 2010-09-01T16:00:50ZChris Lattnersabre@nondot.org2010-09-01T16:00:50Zurn:sha1:5bcb8a6112eca5fb72b39b6b4e608ab1b41e94de
the testcases should be merged.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112711 91177308-0d34-0410-b5e6-96231b3b80d8
We have a chance for an optimization. Consider this code:2010-08-31T22:41:22ZBill Wendlingisanbard@gmail.com2010-08-31T22:41:22Zurn:sha1:43a6c5e2fccadb299c35cb3147d112f706922acd
int x(int t) {
if (t & 256)
return -26;
return 0;
}
We generate this:
tst.w r0, #256
mvn r0, #25
it eq
moveq r0, #0
while gcc generates this:
ands r0, r0, #256
it ne
mvnne r0, #25
bx lr
Scandalous really!
During ISel time, we can look for this particular pattern. One where we have a
"MOVCC" that uses the flag off of a CMPZ that itself is comparing an AND
instruction to 0. Something like this (greatly simplified):
%r0 = ISD::AND ...
ARMISD::CMPZ %r0, 0 @ sets [CPSR]
%r0 = ARMISD::MOVCC 0, -26 @ reads [CPSR]
All we have to do is convert the "ISD::AND" into an "ARM::ANDS" that sets [CPSR]
when it's zero. The zero value will all ready be in the %r0 register and we only
need to change it if the AND wasn't zero. Easy!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112664 91177308-0d34-0410-b5e6-96231b3b80d8
Fix borken test2010-08-30T23:41:49ZAnton Korobeynikovasl@math.spbu.ru2010-08-30T23:41:49Zurn:sha1:5c1919e55da7df42fd1eb392c5636edfd3616689
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112555 91177308-0d34-0410-b5e6-96231b3b80d8
Remove NEON vmovn intrinsic, replacing it with vector truncate operations.2010-08-30T20:02:30ZBob Wilsonbob.wilson@apple.com2010-08-30T20:02:30Zurn:sha1:973a074345add36c046c0f0bfea0156a532ab479
Auto-upgrade the old intrinsic and update tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112507 91177308-0d34-0410-b5e6-96231b3b80d8