llvm/test/Analysis/CostModel/X86, branch testinghttp://llvm.orghttps://git.amat.us/llvm/atom/test/Analysis/CostModel/X86?h=testing2013-03-20T22:01:10ZCorrect cost model for vector shift on AVX22013-03-20T22:01:10ZMichael Liaomichael.liao@intel.com2013-03-20T22:01:10Zurn:sha1:f74e9bf650d7c40d595d3bb60e3c901e2bccec4b
- After moving logic recognizing vector shift with scalar amount from
DAG combining into DAG lowering, we declare to customize all vector
shifts even vector shift on AVX is legal. As a result, the cost model
needs special tuning to identify these legal cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177586 91177308-0d34-0410-b5e6-96231b3b80d8
Optimize sext <4 x i8> and <4 x i16> to <4 x i64>.2013-03-19T18:38:27ZNadav Rotemnrotem@apple.com2013-03-19T18:38:27Zurn:sha1:b05130e1b20ed17ae9d5ab3351933babd27213e1
Patch by Ahmad, Muhammad T <muhammad.t.ahmad@intel.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177421 91177308-0d34-0410-b5e6-96231b3b80d8
X86 cost model: Adjust cost for custom lowered vector multiplies2013-03-02T04:02:52ZArnold Schwaighoferaschwaighofer@apple.com2013-03-02T04:02:52Zurn:sha1:5f0d9dbdf48a9efe16bfadf88e5335f7b9a8ec3f
This matters for example in following matrix multiply:
int **mmult(int rows, int cols, int **m1, int **m2, int **m3) {
int i, j, k, val;
for (i=0; i<rows; i++) {
for (j=0; j<cols; j++) {
val = 0;
for (k=0; k<cols; k++) {
val += m1[i][k] * m2[k][j];
}
m3[i][j] = val;
}
}
return(m3);
}
Taken from the test-suite benchmark Shootout.
We estimate the cost of the multiply to be 2 while we generate 9 instructions
for it and end up being quite a bit slower than the scalar version (48% on my
machine).
Also, properly differentiate between avx1 and avx2. On avx-1 we still split the
vector into 2 128bits and handle the subvector muls like above with 9
instructions.
Only on avx-2 will we have a cost of 9 for v4i64.
I changed the test case in test/Transforms/LoopVectorize/X86/avx1.ll to use an
add instead of a mul because with a mul we now no longer vectorize. I did
verify that the mul would be indeed more expensive when vectorized with 3
kernels:
for (i ...)
r += a[i] * 3;
for (i ...)
m1[i] = m1[i] * 3; // This matches the test case in avx1.ll
and a matrix multiply.
In each case the vectorized version was considerably slower.
radar://13304919
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176403 91177308-0d34-0410-b5e6-96231b3b80d8
Cost model support for lowered math builtins.2013-02-28T19:09:33ZBenjamin Kramerbenny.kra@googlemail.com2013-02-28T19:09:33Zurn:sha1:8611d4449a77ca05e808823bc966573a85da00cb
We make the cost for calling libm functions extremely high as emitting the
calls is expensive and causes spills (on x86) so performance suffers. We still
vectorize important calls like ceilf and friends on SSE4.1. and fabs.
Differential Revision: http://llvm-reviews.chandlerc.com/D466
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176287 91177308-0d34-0410-b5e6-96231b3b80d8
I optimized the following patterns:2013-02-20T12:42:54ZElena Demikhovskyelena.demikhovsky@intel.com2013-02-20T12:42:54Zurn:sha1:52981c4b6016d9f0e295e0771ec0a50dd073b4b3
sext <4 x i1> to <4 x i64>
sext <4 x i8> to <4 x i64>
sext <4 x i16> to <4 x i64>
I'm running Combine on SIGN_EXTEND_IN_REG and revert SEXT patterns:
(sext_in_reg (v4i64 anyext (v4i32 x )), ExtraVT) -> (v4i64 sext (v4i32 sext_in_reg (v4i32 x , ExtraVT)))
The sext_in_reg (v4i32 x) may be lowered to shl+sar operations.
The "sar" does not exist on 64-bit operation, so lowering sext_in_reg (v4i64 x) has no vector solution.
I also added a cost of this operations to the AVX costs table.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175619 91177308-0d34-0410-b5e6-96231b3b80d8
ARM cost model: Address computation in vector mem ops not free2013-02-08T14:50:48ZArnold Schwaighoferaschwaighofer@apple.com2013-02-08T14:50:48Zurn:sha1:fb55a8fd7c38aa09d9c243d48a8a72d890f36a3d
Adds a function to target transform info to query for the cost of address
computation. The cost model analysis pass now also queries this interface.
The code in LoopVectorize adds the cost of address computation as part of the
memory instruction cost calculation. Only there, we know whether the instruction
will be scalarized or not.
Increase the penality for inserting in to D registers on swift. This becomes
necessary because we now always assume that address computation has a cost and
three is a closer value to the architecture.
radar://13097204
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174713 91177308-0d34-0410-b5e6-96231b3b80d8
We are not ready to estimate the cost of integer expansions based on the number of parts. This test is too noisy.2012-12-23T09:11:07ZNadav Rotemnrotem@apple.com2012-12-23T09:11:07Zurn:sha1:f85ec865f0f803273ab38e3b1a19fe185c7e88ac
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170999 91177308-0d34-0410-b5e6-96231b3b80d8
Improve the X86 cost model for loads and stores.2012-12-21T01:33:59ZNadav Rotemnrotem@apple.com2012-12-21T01:33:59Zurn:sha1:f5637c399711e37287e01f9d9ca9ce7cd2f3d14f
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170830 91177308-0d34-0410-b5e6-96231b3b80d8
Reverse order of checking SSE level when calculating compare cost, so we check2012-12-18T22:57:56ZJakub Staszakkubastaszak@gmail.com2012-12-18T22:57:56Zurn:sha1:270bfbd3d1fb42000b23e5747ac7957b0e9fcab8
AVX2 before AVX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170464 91177308-0d34-0410-b5e6-96231b3b80d8
Cost Model: change the default cost of control flow instructions (br / ret / ...) to zero.2012-12-05T21:21:26ZNadav Rotemnrotem@apple.com2012-12-05T21:21:26Zurn:sha1:0602bb46596485b43fa8b86abbc8485d502025ce
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169423 91177308-0d34-0410-b5e6-96231b3b80d8