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<title>llvm/lib, branch testing</title>
<subtitle>http://llvm.org</subtitle>
<id>https://git.amat.us/llvm/atom/lib?h=testing</id>
<link rel='self' href='https://git.amat.us/llvm/atom/lib?h=testing'/>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/'/>
<updated>2013-03-22T05:47:44Z</updated>
<entry>
<title>Reorder the DIFile field in DILexicalBlock to become a prefix common with other DIScopes</title>
<updated>2013-03-22T05:47:44Z</updated>
<author>
<name>David Blaikie</name>
<email>dblaikie@gmail.com</email>
</author>
<published>2013-03-22T05:47:44Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=c204410d6bc435e7cb8ea768759a54135e8e92b5'/>
<id>urn:sha1:c204410d6bc435e7cb8ea768759a54135e8e92b5</id>
<content type='text'>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177703 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Revert r177543: Add timing of the IR parsing code with a new</title>
<updated>2013-03-22T02:20:34Z</updated>
<author>
<name>Chandler Carruth</name>
<email>chandlerc@gmail.com</email>
</author>
<published>2013-03-22T02:20:34Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=f0b0f1f9d97f4cf4d2f00c60fbc3d377a93465f8'/>
<id>urn:sha1:f0b0f1f9d97f4cf4d2f00c60fbc3d377a93465f8</id>
<content type='text'>
-time-ir-parsing flag

This breaks the layering of the Support library. We can't add an
implementation side to IRReader because it refers directly to entities
only accessible as part of the IR, AsmParser, and BitcodeReader
libraries. It can only be used in a context where all of those libraries
will be available.

We'll need to find some other way to get this functionality, and
hopefully solve the long-standing layering problem of IRReader.h...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177695 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Fix the invalid opcode for Mips branch instructions in the assembler</title>
<updated>2013-03-22T00:29:10Z</updated>
<author>
<name>Jack Carter</name>
<email>jack.carter@imgtec.com</email>
</author>
<published>2013-03-22T00:29:10Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=d3107fbc54a5b5156f0aabc8788724f1469eb9df'/>
<id>urn:sha1:d3107fbc54a5b5156f0aabc8788724f1469eb9df</id>
<content type='text'>
For mips a branch an 18-bit signed offset (the 16-bit 
offset field shifted left 2 bits) is added to the 
address of the instruction following the branch 
(not the branch itself), in the branch delay slot, 
to form a PC-relative effective target address. 

Previously, the code generator did not perform the 
shift of the immediate branch offset which resulted 
in wrong instruction opcode. This patch fixes the issue.

Contributor: Vladimir Medic



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177687 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>This patch that enables the Mips assembler to use symbols for offset for instructions</title>
<updated>2013-03-22T00:05:30Z</updated>
<author>
<name>Jack Carter</name>
<email>jack.carter@imgtec.com</email>
</author>
<published>2013-03-22T00:05:30Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=25df6a93f3324bd30f44dcb95fd17aff0a92d438'/>
<id>urn:sha1:25df6a93f3324bd30f44dcb95fd17aff0a92d438</id>
<content type='text'>
This patch uses the generated instruction info tables to 
identify memory/load store instructions.
After successful matching and based on the operand type 
and size, it generates additional instructions to the output.

Contributor: Vladimir Medic



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177685 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Remove the G8RC_NOX0_and_GPRC_NOR0 PPC register class</title>
<updated>2013-03-21T23:45:03Z</updated>
<author>
<name>Hal Finkel</name>
<email>hfinkel@anl.gov</email>
</author>
<published>2013-03-21T23:45:03Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=7697370adff8983e2a3de493362f0d8c9f9b0e17'/>
<id>urn:sha1:7697370adff8983e2a3de493362f0d8c9f9b0e17</id>
<content type='text'>
As Jakob pointed out in his review of r177423, having a shared ZERO
register between the 32- and 64-bit register classes causes this
odd G8RC_NOX0_and_GPRC_NOR0 class to be created. As recommended,
this adds a ZERO8 register which differentiates the 32- and 64-bit
zeros.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177683 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Always forward 'resume' instructions to the outter landing pad.</title>
<updated>2013-03-21T23:30:12Z</updated>
<author>
<name>Bill Wendling</name>
<email>isanbard@gmail.com</email>
</author>
<published>2013-03-21T23:30:12Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=d9ff8c83d137586d8c06f98bdf8adbf0d1fa79ca'/>
<id>urn:sha1:d9ff8c83d137586d8c06f98bdf8adbf0d1fa79ca</id>
<content type='text'>
How did this ever work?

Basically, if you have a function that's inlined into the caller, it may not
have any 'call' instructions, but any 'resume' instructions it may have should
still be forwarded to the outer (caller's) landing pad. This requires that all
of the 'landingpad' instructions in the callee have their clauses merged with
the caller's outer 'landingpad' instruction (hence the bit of ugly code in the
`forwardResume' method).

Testcase in a follow commit to the test-suite repository.

&lt;rdar://problem/13360379&gt; &amp; PR15555


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177680 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Fix a register-class comparison bug in PPCCTRLoops</title>
<updated>2013-03-21T23:23:34Z</updated>
<author>
<name>Hal Finkel</name>
<email>hfinkel@anl.gov</email>
</author>
<published>2013-03-21T23:23:34Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=3ea1b064a0b9c3d161b0f77a9e957970f98907ab'/>
<id>urn:sha1:3ea1b064a0b9c3d161b0f77a9e957970f98907ab</id>
<content type='text'>
Thanks to Jakob for isolating the underlying problem from the
test case in r177423. The original commit had introduced
asymmetric copy operations, but these turned out to be a work-around
to the real problem (the use of == instead of hasSubClassEq in PPCCTRLoops).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177679 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Refactor the filename/directory information in DISubprogram to refer directly to the pair rather than the DIFile.</title>
<updated>2013-03-21T23:08:34Z</updated>
<author>
<name>David Blaikie</name>
<email>dblaikie@gmail.com</email>
</author>
<published>2013-03-21T23:08:34Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=bb4e619cd9ff34708e3baaf0aac70275a917e0ba'/>
<id>urn:sha1:bb4e619cd9ff34708e3baaf0aac70275a917e0ba</id>
<content type='text'>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177677 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Add a query to tell if a landing pad has a catch-all.</title>
<updated>2013-03-21T23:01:03Z</updated>
<author>
<name>Bill Wendling</name>
<email>isanbard@gmail.com</email>
</author>
<published>2013-03-21T23:01:03Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=8233050895f781befc1d4165435d0fff605b6b70'/>
<id>urn:sha1:8233050895f781befc1d4165435d0fff605b6b70</id>
<content type='text'>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177675 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Move the DIFile in DISubprogram to the beginning to be a common prefix along with other DIScopes</title>
<updated>2013-03-21T22:29:36Z</updated>
<author>
<name>David Blaikie</name>
<email>dblaikie@gmail.com</email>
</author>
<published>2013-03-21T22:29:36Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=ced228dec30f088367d622720d6ccf7a22cd11e4'/>
<id>urn:sha1:ced228dec30f088367d622720d6ccf7a22cd11e4</id>
<content type='text'>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177674 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
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