llvm/lib/Target, branch masterhttp://llvm.orghttps://git.amat.us/llvm/atom/lib/Target?h=master2013-05-14T02:13:45ZRemoved an unnamed namespace and forgot to make two of the functions inside2013-05-14T02:13:45ZReed Kotlerrkotler@mips.com2013-05-14T02:13:45Zurn:sha1:5427aa88d5930655ef9e958446489acc1bf9a160
"static".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181754 91177308-0d34-0410-b5e6-96231b3b80d8
This is the first of three patches which creates stubs used for2013-05-14T02:00:24ZReed Kotlerrkotler@mips.com2013-05-14T02:00:24Zurn:sha1:eafa96485a6c3ce0de4f511ed080a64a7a44f2bb
Mips16/32 floating point interoperability.
When Mips16 code calls external functions that would normally have some
of its parameters or return values passed in floating point registers,
it needs (Mips32) helper functions to do this because while in Mips16 mode
there is no ability to access the floating point registers.
In Pic mode, this is done with a set of predefined functions in libc.
This case is already handled in llvm for Mips16.
In static relocation mode, for efficiency reasons, the compiler generates
stubs that the linker will use if it turns out that the external function
is a Mips32 function. (If it's Mips16, then it does not need the helper
stubs).
These stubs are identically named and the linker knows about these tricks
and will not create multiple copies and will delete them if they are not
needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181753 91177308-0d34-0410-b5e6-96231b3b80d8
Mips assembler: Assembler macro ADDIU $rs,imm2013-05-13T20:26:46ZJack Carterjack.carter@imgtec.com2013-05-13T20:26:46Zurn:sha1:f4a1377322a9234c17b1d324c47248bdb5f62158
This patch adds alias for addiu instruction which enables following syntax:
addiu $rs,imm
The macro is translated as:
addiu $rs,$rs,imm
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181729 91177308-0d34-0410-b5e6-96231b3b80d8
Fix goofy commentary in PPCTargetObjectFile.cpp.2013-05-13T19:40:36ZBill Schmidtwschmidt@linux.vnet.ibm.com2013-05-13T19:40:36Zurn:sha1:59b078fc56e64b9b2d13521670648034cd870c0f
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181725 91177308-0d34-0410-b5e6-96231b3b80d8
PPC64: Constant initializers with dynamic relocations go in .data.rel.ro.2013-05-13T19:34:37ZBill Schmidtwschmidt@linux.vnet.ibm.com2013-05-13T19:34:37Zurn:sha1:240b9b6078cdf8048945107b4ff7d517729dab96
This fixes warning messages observed in the oggenc application test in
projects/test-suite. Special handling is needed for the 64-bit
PowerPC SVR4 ABI when a constant is initialized with a pointer to a
function in a shared library. Because a function address is
implemented as the address of a function descriptor, the use of copy
relocations can lead to problems with initialization. GNU ld
therefore replaces copy relocations with dynamic relocations to be
resolved by the dynamic linker. This means the constant cannot reside
in the read-only data section, but instead belongs in .data.rel.ro,
which is designed for constants containing dynamic relocations.
The implementation creates a class PPC64LinuxTargetObjectFile
inheriting from TargetLoweringObjectFileELF, which behaves like its
parent except to place constants of this sort into .data.rel.ro.
The test case is reduced from the oggenc application.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181723 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Add option -mno-ldc1-sdc1.2013-05-13T18:23:35ZAkira Hatanakaahatanaka@mips.com2013-05-13T18:23:35Zurn:sha1:42f562a1694d24b41f36bbb4d4a086a2a470c625
This option is used when the user wants to avoid emitting double precision FP
loads and stores. Double precision FP loads and stores are expanded to single
precision instructions after register allocation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181718 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Define a helper function which creates an instruction with the same2013-05-13T17:57:42ZAkira Hatanakaahatanaka@mips.com2013-05-13T17:57:42Zurn:sha1:151687cb8c4fc65fefcd8964a0c3d77680e90a5c
operands as the prototype instruction but with a different opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181714 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Rename functions. No functionality changes.2013-05-13T17:43:19ZAkira Hatanakaahatanaka@mips.com2013-05-13T17:43:19Zurn:sha1:6daba286836e6fb2351e7ebc248e18a5c80e8a31
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181713 91177308-0d34-0410-b5e6-96231b3b80d8
Remove unused fields and arguments.2013-05-13T14:34:48ZRafael Espindolarafael.espindola@gmail.com2013-05-13T14:34:48Zurn:sha1:6eb70ac034a4b23a129fa674dd9852b6d3a615c8
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181706 91177308-0d34-0410-b5e6-96231b3b80d8
The purpose of the patch is to fix the syntax of ARM mrc and mrc2 instructions when they are used to write to the APSR. In this case, the destination operand should be APSR_nzcv, and the encoding of the target should be 0b1111 (same as for PC). In pre-UAL syntax, this form used the PC register as a textual target. This is still allowed for backward compatibility.2013-05-13T14:10:04ZMihai Popamihail.popa@gmail.com2013-05-13T14:10:04Zurn:sha1:f86e436fb95670ed110818fefa403f21ae104639
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181705 91177308-0d34-0410-b5e6-96231b3b80d8