<feed xmlns='http://www.w3.org/2005/Atom'>
<title>llvm/lib/Target/XCore, branch stable</title>
<subtitle>http://llvm.org</subtitle>
<id>https://git.amat.us/llvm/atom/lib/Target/XCore?h=stable</id>
<link rel='self' href='https://git.amat.us/llvm/atom/lib/Target/XCore?h=stable'/>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/'/>
<updated>2013-03-22T23:32:27Z</updated>
<entry>
<title>Allow the register scavenger to spill multiple registers</title>
<updated>2013-03-22T23:32:27Z</updated>
<author>
<name>Hal Finkel</name>
<email>hfinkel@anl.gov</email>
</author>
<published>2013-03-22T23:32:27Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=dc3beb90178fc316f63790812b22201884eaa017'/>
<id>urn:sha1:dc3beb90178fc316f63790812b22201884eaa017</id>
<content type='text'>
This patch lets the register scavenger make use of multiple spill slots in
order to guarantee that it will be able to provide multiple registers
simultaneously.

To support this, the RS's API has changed slightly: setScavengingFrameIndex /
getScavengingFrameIndex have been replaced by addScavengingFrameIndex /
isScavengingFrameIndex / getScavengingFrameIndices.

In forthcoming commits, the PowerPC backend will use this capability in order
to implement the spilling of condition registers, and some special-purpose
registers, without relying on r0 being reserved. In some cases, spilling these
registers requires two GPRs: one for addressing and one to hold the value being
transferred.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177774 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>DAGCombiner: Use correct value type for checking legality of BR_CC v3</title>
<updated>2013-03-08T15:36:57Z</updated>
<author>
<name>Tom Stellard</name>
<email>thomas.stellard@amd.com</email>
</author>
<published>2013-03-08T15:36:57Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=3ef5383b3537a420c5e2ab3e657c378e5185549d'/>
<id>urn:sha1:3ef5383b3537a420c5e2ab3e657c378e5185549d</id>
<content type='text'>
LegalizeDAG.cpp uses the value of the comparison operands when checking
the legality of BR_CC, so DAGCombiner should do the same.

v2:
  - Expand more BR_CC value types for NVPTX

v3:
  - Expand correct BR_CC value types for Hexagon, Mips, and XCore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176694 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Fix PR10475</title>
<updated>2013-03-01T18:40:30Z</updated>
<author>
<name>Michael Liao</name>
<email>michael.liao@intel.com</email>
</author>
<published>2013-03-01T18:40:30Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=a6b20ced765b67a85d9219d0c8547fc9c133e14f'/>
<id>urn:sha1:a6b20ced765b67a85d9219d0c8547fc9c133e14f</id>
<content type='text'>
- ISD::SHL/SRL/SRA must have either both scalar or both vector operands
  but TLI.getShiftAmountTy() so far only return scalar type. As a
  result, backend logic assuming that breaks.
- Rename the original TLI.getShiftAmountTy() to
  TLI.getScalarShiftAmountTy() and re-define TLI.getShiftAmountTy() to
  return target-specificed scalar type or the same vector type as the
  1st operand.
- Fix most TICG logic assuming TLI.getShiftAmountTy() a simple scalar
  type.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176364 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Move the eliminateCallFramePseudoInstr method from TargetRegisterInfo</title>
<updated>2013-02-21T20:05:00Z</updated>
<author>
<name>Eli Bendersky</name>
<email>eliben@google.com</email>
</author>
<published>2013-02-21T20:05:00Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=700ed80d3da5e98e05ceb90e9bfb66058581a6db'/>
<id>urn:sha1:700ed80d3da5e98e05ceb90e9bfb66058581a6db</id>
<content type='text'>
to TargetFrameLowering, where it belongs. Incidentally, this allows us
to delete some duplicated (and slightly different!) code in TRI.

There are potentially other layering problems that can be cleaned up
as a result, or in a similar manner.

The refactoring was OK'd by Anton Korobeynikov on llvmdev.

Note: this touches the target interfaces, so out-of-tree targets may
be affected.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175788 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Update TargetLowering ivars for name policy.</title>
<updated>2013-02-20T21:13:59Z</updated>
<author>
<name>Jim Grosbach</name>
<email>grosbach@apple.com</email>
</author>
<published>2013-02-20T21:13:59Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=3450f800aa65c91f0496816ba6061a422a74c1fe'/>
<id>urn:sha1:3450f800aa65c91f0496816ba6061a422a74c1fe</id>
<content type='text'>
http://llvm.org/docs/CodingStandards.html#name-types-functions-variables-and-enumerators-properly

ivars should be camel-case and start with an upper-case letter. A few in
TargetLowering were starting with a lower-case letter.

No functional change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175667 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>[XCore] Add missing 2r instructions.</title>
<updated>2013-02-17T22:38:05Z</updated>
<author>
<name>Richard Osborne</name>
<email>richard@xmos.com</email>
</author>
<published>2013-02-17T22:38:05Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=8dc741e400213ea8183e09626f0d1f45f14e044f'/>
<id>urn:sha1:8dc741e400213ea8183e09626f0d1f45f14e044f</id>
<content type='text'>
These instructions are not targeted by the compiler but it is needed for
the MC layer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175407 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>[XCore] Add TSETR instruction.</title>
<updated>2013-02-17T22:32:41Z</updated>
<author>
<name>Richard Osborne</name>
<email>richard@xmos.com</email>
</author>
<published>2013-02-17T22:32:41Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=763c858edeb76173ee4ef5ab9bf7d750db5d8c4f'/>
<id>urn:sha1:763c858edeb76173ee4ef5ab9bf7d750db5d8c4f</id>
<content type='text'>
This instruction is not targeted by the compiler but it is needed for the
MC layer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175406 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>[XCore] Add missing u10 / lu10 instructions.</title>
<updated>2013-02-17T20:44:48Z</updated>
<author>
<name>Richard Osborne</name>
<email>richard@xmos.com</email>
</author>
<published>2013-02-17T20:44:48Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=a970dde9060d8994c242bd186bb3636d2caf22d2'/>
<id>urn:sha1:a970dde9060d8994c242bd186bb3636d2caf22d2</id>
<content type='text'>
These instructions are not targeted by the compiler but they are
needed for the MC layer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175404 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>[XCore] Add missing u6 / lu6 instructions.</title>
<updated>2013-02-17T20:43:17Z</updated>
<author>
<name>Richard Osborne</name>
<email>richard@xmos.com</email>
</author>
<published>2013-02-17T20:43:17Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=cbe6c88b6811e4641629d111f941879982362fe8'/>
<id>urn:sha1:cbe6c88b6811e4641629d111f941879982362fe8</id>
<content type='text'>
These instructions are not targeted by the compiler but they are
needed for the MC layer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175403 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Move MRI liveouts to XCore return instructions.</title>
<updated>2013-02-05T18:21:46Z</updated>
<author>
<name>Jakob Stoklund Olesen</name>
<email>stoklund@2pi.dk</email>
</author>
<published>2013-02-05T18:21:46Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=0873bc84190df92b474cb92ec4a7e36fbcb610f9'/>
<id>urn:sha1:0873bc84190df92b474cb92ec4a7e36fbcb610f9</id>
<content type='text'>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174414 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
</feed>
