llvm/lib/Target/XCore, branch release_33http://llvm.orghttps://git.amat.us/llvm/atom/lib/Target/XCore?h=release_332013-05-05T13:36:53Z[XCore] Add LDAPB instructions.2013-05-05T13:36:53ZRichard Osbornerichard@xmos.com2013-05-05T13:36:53Zurn:sha1:589ddc9887406ddfd5a2661b567057faad7a22cc
With the change the disassembler now supports the XCore ISA in its
entirety.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181155 91177308-0d34-0410-b5e6-96231b3b80d8
[XCore] Update LDAP to use pcrel_imm.2013-05-05T13:33:10ZRichard Osbornerichard@xmos.com2013-05-05T13:33:10Zurn:sha1:fae63389d9a7fb2d0c544732ae5634563bd274aa
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181154 91177308-0d34-0410-b5e6-96231b3b80d8
[XCore] Rename calltarget -> pcrel_imm.2013-05-05T13:29:02ZRichard Osbornerichard@xmos.com2013-05-05T13:29:02Zurn:sha1:24aeab3d8a4830b333f6453c16c14f7f87e3cee4
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181153 91177308-0d34-0410-b5e6-96231b3b80d8
[XCore] Add BLRB instructions.2013-05-05T13:24:16ZRichard Osbornerichard@xmos.com2013-05-05T13:24:16Zurn:sha1:c601bd69d5c7fcd3bf9946e8a8a1bd1f9ab6642b
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181152 91177308-0d34-0410-b5e6-96231b3b80d8
[XCore] Remove '-' from back branch asm syntax.2013-05-05T13:20:22ZRichard Osbornerichard@xmos.com2013-05-05T13:20:22Zurn:sha1:1114b0ec15aaa22dfc0ce582820cea556600d103
Instead operands are treated as negative immediates
where the sign bit is implicit in the instruction
encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181151 91177308-0d34-0410-b5e6-96231b3b80d8
Fix buildbot failure on 64 bit linux due to std::max() having different2013-05-04T17:41:01ZRichard Osbornerichard@xmos.com2013-05-04T17:41:01Zurn:sha1:7153a30610e78c5cd1347a31f3a90dde2f335f37
operand types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181128 91177308-0d34-0410-b5e6-96231b3b80d8
[XCore] Remove unused operand type.2013-05-04T17:30:05ZRichard Osbornerichard@xmos.com2013-05-04T17:30:05Zurn:sha1:43c7abee14b08b4d8595e634f2fd91be79327ccb
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181127 91177308-0d34-0410-b5e6-96231b3b80d8
[XCore] Make use of the target independent global address offset folding.2013-05-04T17:24:33ZRichard Osbornerichard@xmos.com2013-05-04T17:24:33Zurn:sha1:6ffbf6ea8fe7fbe2166b07a88004baac163aa3c5
This let us to remove some custom code that matched constant offsets
from globals at instruction selection time as a special addressing mode.
No intended functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181126 91177308-0d34-0410-b5e6-96231b3b80d8
[XCore] Simplify code that checks for an aligned base plus a constant.2013-05-04T17:17:10ZRichard Osbornerichard@xmos.com2013-05-04T17:17:10Zurn:sha1:40827bc716e9eda3e70460207696f2ec10dd67ad
The code now makes use of ComputeMaskedBits,
SelectionDAG::isBaseWithConstantOffset and TargetLowering::isGAPlusOffset
where appropriate reducing the amount of logic needed in XCoreISelLowering.
No intended functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181125 91177308-0d34-0410-b5e6-96231b3b80d8
[XCore] Move lowering of thread local storage to a separate pass.2013-05-04T17:01:55ZRichard Osbornerichard@xmos.com2013-05-04T17:01:55Zurn:sha1:597432fbe53bda0069b0ad13e5ad57ae0ee7ee45
Thread local storage is not supported by the XMOS linker so we handle
thread local variables by lowering the variable to an array of n elements
(where n is the number of hardware threads per core, currently 8
for all XMOS devices) indexed by the the current thread ID.
Previously this lowering was spread across the XCoreISelLowering and the
XCoreAsmPrinter classes. Moving this to a separate pass should be much
cleaner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181124 91177308-0d34-0410-b5e6-96231b3b80d8