llvm/lib/Target/XCore, branch release_30http://llvm.orghttps://git.amat.us/llvm/atom/lib/Target/XCore?h=release_302011-10-11T12:55:35ZImplement the emitFrameIndexDebugValue and getDebugValueLocation hooks.2011-10-11T12:55:35ZRichard Osbornerichard@xmos.com2011-10-11T12:55:35Zurn:sha1:6c6f28ffe42d06655f5977bd0d01214e32de93a5
This fixes an assert due to the operands of the DBG_VALUE instruction not
being as expected (PR11105).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141666 91177308-0d34-0410-b5e6-96231b3b80d8
Build system infrastructure for multiple tblgens.2011-10-06T01:51:51ZPeter Collingbournepeter@pcc.me.uk2011-10-06T01:51:51Zurn:sha1:de8f33c199f3bf2049b0b732169f2bd8717469c6
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141266 91177308-0d34-0410-b5e6-96231b3b80d8
Fix 80 column violations.2011-09-23T16:28:10ZRichard Osbornerichard@xmos.com2011-09-23T16:28:10Zurn:sha1:0353dab90ec502b02cbf2cee845e07d51627248b
Original patch by Liu.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140385 91177308-0d34-0410-b5e6-96231b3b80d8
Associate a MemOperand with LDWCP nodes introduced during ISel.2011-09-12T14:43:23ZRichard Osbornerichard@xmos.com2011-09-12T14:43:23Zurn:sha1:a1d16b53e847a97846ad5df293ae1cfc3091a092
This information is required if we want LDWCP to be hoisted out of loops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139495 91177308-0d34-0410-b5e6-96231b3b80d8
Mark LDWCP as having no side effects.2011-09-12T14:41:31ZRichard Osbornerichard@xmos.com2011-09-12T14:41:31Zurn:sha1:2cb6c1bd20ddcf27da5fb50a8a74a97a9d3010fb
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139494 91177308-0d34-0410-b5e6-96231b3b80d8
Add codegen support for vector select (in the IR this means a select2011-09-06T19:07:46ZDuncan Sandsbaldrick@free.fr2011-09-06T19:07:46Zurn:sha1:28b77e968d2b01fc9da724762bd8ddcd80650e32
with a vector condition); such selects become VSELECT codegen nodes.
This patch also removes VSETCC codegen nodes, unifying them with SETCC
nodes (codegen was actually often using SETCC for vector SETCC already).
This ensures that various DAG combiner optimizations kick in for vector
comparisons. Passes dragonegg bootstrap with no testsuite regressions
(nightly testsuite as well as "make check-all"). Patch mostly by
Nadav Rotem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139159 91177308-0d34-0410-b5e6-96231b3b80d8
Split the init.trampoline intrinsic, which currently combines GCC's2011-09-06T13:37:06ZDuncan Sandsbaldrick@free.fr2011-09-06T13:37:06Zurn:sha1:4a544a79bd735967f1d33fe675ae4566dbd17813
init.trampoline and adjust.trampoline intrinsics, into two intrinsics
like in GCC. While having one combined intrinsic is tempting, it is
not natural because typically the trampoline initialization needs to
be done in one function, and the result of adjust trampoline is needed
in a different (nested) function. To get around this llvm-gcc hacks the
nested function lowering code to insert an additional parent variable
holding the adjust.trampoline result that can be accessed from the child
function. Dragonegg doesn't have the luxury of tweaking GCC code, so it
stored the result of adjust.trampoline in the memory GCC set aside for
the trampoline itself (this is always available in the child function),
and set up some new memory (using an alloca) to hold the trampoline.
Unfortunately this breaks Go which allocates trampoline memory on the
heap and wants to use it even after the parent has exited (!). Rather
than doing even more hacks to get Go working, it seemed best to just use
two intrinsics like in GCC. Patch mostly by Sanjoy Das.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139140 91177308-0d34-0410-b5e6-96231b3b80d8
Move TargetRegistry and TargetSelect from Target to Support where they belong.2011-08-24T18:08:43ZEvan Chengevan.cheng@apple.com2011-08-24T18:08:43Zurn:sha1:3e74d6fdd248e20a280f1dff3da9a6c689c2c4c3
These are strictly utilities for registering targets and components.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138450 91177308-0d34-0410-b5e6-96231b3b80d8
Add Uses=[SP] to call instructions. This fixes a miscompilation with a2011-08-24T13:32:43ZRichard Osbornerichard@xmos.com2011-08-24T13:32:43Zurn:sha1:8f9c5cca4feb71471dda44d9ba39a0ca644ddd6e
variable sized alloca.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138433 91177308-0d34-0410-b5e6-96231b3b80d8
Some refactoring so TargetRegistry.h no longer has to include any files2011-08-23T20:15:21ZEvan Chengevan.cheng@apple.com2011-08-23T20:15:21Zurn:sha1:7801136b95d1fbe515b9655b73ada39b05a33559
from MC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138367 91177308-0d34-0410-b5e6-96231b3b80d8