llvm/lib/Target/XCore/Disassembler, branch testing http://llvm.org https://git.amat.us/llvm/atom/lib/Target/XCore/Disassembler?h=testing 2013-02-17T22:38:05Z [XCore] Add missing 2r instructions. 2013-02-17T22:38:05Z Richard Osborne richard@xmos.com 2013-02-17T22:38:05Z urn:sha1:8dc741e400213ea8183e09626f0d1f45f14e044f These instructions are not targeted by the compiler but it is needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175407 91177308-0d34-0410-b5e6-96231b3b80d8 [XCore] Add TSETR instruction. 2013-02-17T22:32:41Z Richard Osborne richard@xmos.com 2013-02-17T22:32:41Z urn:sha1:763c858edeb76173ee4ef5ab9bf7d750db5d8c4f This instruction is not targeted by the compiler but it is needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175406 91177308-0d34-0410-b5e6-96231b3b80d8 [XCore] Add missing l2rus instructions. 2013-01-27T22:28:30Z Richard Osborne richard@xmos.com 2013-01-27T22:28:30Z urn:sha1:970a479c02a418726950580e13136acd2a2dc13f These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173634 91177308-0d34-0410-b5e6-96231b3b80d8 Add instruction encodings / disassembly support for l4r instructions. 2013-01-25T21:55:32Z Richard Osborne richard@xmos.com 2013-01-25T21:55:32Z urn:sha1:c47bd9899b639c3384268f871009259c2a94fba4 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173501 91177308-0d34-0410-b5e6-96231b3b80d8 Use the correct format in the STW / SETPSC instruction names. 2013-01-25T21:25:12Z Richard Osborne richard@xmos.com 2013-01-25T21:25:12Z urn:sha1:1f375e5bc78647f9b29564eafdc907250ccd91ed git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173494 91177308-0d34-0410-b5e6-96231b3b80d8 Add instruction encodings / disassembly support for l5r instructions. 2013-01-25T20:20:07Z Richard Osborne richard@xmos.com 2013-01-25T20:20:07Z urn:sha1:3b6a5eefe0ab2199bc69094b390b736ae332b905 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173479 91177308-0d34-0410-b5e6-96231b3b80d8 Add instruction encodings / disassembly support for l6r instructions. 2013-01-23T20:08:11Z Richard Osborne richard@xmos.com 2013-01-23T20:08:11Z urn:sha1:9e6a5a37460ff82ad4e3a7aea1c45e2c934ab25b git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173288 91177308-0d34-0410-b5e6-96231b3b80d8 Add instruction encoding / disassembly support for ru6 / lru6 instructions. 2013-01-21T20:42:16Z Richard Osborne richard@xmos.com 2013-01-21T20:42:16Z urn:sha1:9b709f8b3f3fa6e9bfb5007b70e096f6192f3ef8 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173085 91177308-0d34-0410-b5e6-96231b3b80d8 Add instruction encodings / disassembly support for l2rus instructions. 2013-01-20T18:51:15Z Richard Osborne richard@xmos.com 2013-01-20T18:51:15Z urn:sha1:b853c415c663c752c669cb191cea95542c1d21f6 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172987 91177308-0d34-0410-b5e6-96231b3b80d8 Add instruction encodings / disassembly support for l3r instructions. 2013-01-20T18:37:49Z Richard Osborne richard@xmos.com 2013-01-20T18:37:49Z urn:sha1:c78ec6b6bc05572aed6af1eee4349d76a68ded18 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172986 91177308-0d34-0410-b5e6-96231b3b80d8