llvm/lib/Target/X86, branch testing http://llvm.org https://git.amat.us/llvm/atom/lib/Target/X86?h=testing 2013-03-21T00:07:17Z Add a WriteMicrocoded for ancient microcoded instructions. 2013-03-21T00:07:17Z Jakob Stoklund Olesen stoklund@2pi.dk 2013-03-21T00:07:17Z urn:sha1:c1ea2c5d6d5870b44c2021729c2e8a627753e83b git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177611 91177308-0d34-0410-b5e6-96231b3b80d8 Model prefetches and barriers as loads. 2013-03-20T23:09:53Z Jakob Stoklund Olesen stoklund@2pi.dk 2013-03-20T23:09:53Z urn:sha1:3c987aead275e5e4c654650fd7199c4acf1d18cf It's not yet clear if these instructions need a more careful model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177599 91177308-0d34-0410-b5e6-96231b3b80d8 Add a catch-all WriteSystem SchedWrite type. 2013-03-20T23:09:50Z Jakob Stoklund Olesen stoklund@2pi.dk 2013-03-20T23:09:50Z urn:sha1:eab5f7678b7024d275087734f03031d9f88ef08c This is used for all the expensive system instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177598 91177308-0d34-0410-b5e6-96231b3b80d8 Annotate the remaining SSE MOV instructions. 2013-03-20T22:37:16Z Jakob Stoklund Olesen stoklund@2pi.dk 2013-03-20T22:37:16Z urn:sha1:dcb4d349b683d9b52b084c94c9941020ebef4bc2 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177592 91177308-0d34-0410-b5e6-96231b3b80d8 Annotate SSE horizontal and integer instructions. 2013-03-20T22:37:13Z Jakob Stoklund Olesen stoklund@2pi.dk 2013-03-20T22:37:13Z urn:sha1:2e9aadda63b6567a24345dd9c57d7275453464dc git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177591 91177308-0d34-0410-b5e6-96231b3b80d8 Correct cost model for vector shift on AVX2 2013-03-20T22:01:10Z Michael Liao michael.liao@intel.com 2013-03-20T22:01:10Z urn:sha1:f74e9bf650d7c40d595d3bb60e3c901e2bccec4b - After moving logic recognizing vector shift with scalar amount from DAG combining into DAG lowering, we declare to customize all vector shifts even vector shift on AVX is legal. As a result, the cost model needs special tuning to identify these legal cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177586 91177308-0d34-0410-b5e6-96231b3b80d8 Add some missing SSE annotations. 2013-03-20T16:56:39Z Jakob Stoklund Olesen stoklund@2pi.dk 2013-03-20T16:56:39Z urn:sha1:279ad470b679be919ca220e2b664d9cf94055bc5 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177540 91177308-0d34-0410-b5e6-96231b3b80d8 Annotate remaining IIC_BIN_* instructions. 2013-03-20T16:56:36Z Jakob Stoklund Olesen stoklund@2pi.dk 2013-03-20T16:56:36Z urn:sha1:374a204f02238ee7549b0c3d5cb6088132eb74b5 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177539 91177308-0d34-0410-b5e6-96231b3b80d8 Fix PR15296 2013-03-20T02:33:21Z Michael Liao michael.liao@intel.com 2013-03-20T02:33:21Z urn:sha1:42317ccb5fed9de14118e1c48417b814d94e3d28 - Move SRA/SRL/SHL lowering support from DAG combination to DAG lowering to support extended 256-bit integer in AVX but not AVX2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177478 91177308-0d34-0410-b5e6-96231b3b80d8 Mark all variable shifts needing customizing 2013-03-20T02:28:20Z Michael Liao michael.liao@intel.com 2013-03-20T02:28:20Z urn:sha1:5c5f1908f0abd187620d3fc660bf74fe6a8c531b - Prepare moving logic from DAG combining into DAG lowering. There's no functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177477 91177308-0d34-0410-b5e6-96231b3b80d8