llvm/lib/Target/X86/MCTargetDesc, branch testinghttp://llvm.orghttps://git.amat.us/llvm/atom/lib/Target/X86/MCTargetDesc?h=testing2013-03-16T03:44:31ZAdd X86 code emitter support AVX encoded MRMDestReg instructions.2013-03-16T03:44:31ZCraig Toppercraig.topper@gmail.com2013-03-16T03:44:31Zurn:sha1:8647750dfbae36a7a49767202a2e363ffc861e5a
Previously we weren't skipping the VVVV encoded register. Based on patch by Michael Liao.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177221 91177308-0d34-0410-b5e6-96231b3b80d8
Fix a bug in the calculation of the VEX.B bit for FMA4 rr with the VEX.W bit set. The VEX.B was being calculated from the wrong operand. Fixes at least some portion of PR14185.2013-03-14T07:40:52ZCraig Toppercraig.topper@gmail.com2013-03-14T07:40:52Zurn:sha1:9d3f3c5f400578855f6f7b71670cb8514b4fac0f
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177014 91177308-0d34-0410-b5e6-96231b3b80d8
The current X86 NOP padding uses one long NOP followed by the remainder in2013-03-05T00:02:23ZDavid Sehrsehr@google.com2013-03-05T00:02:23Zurn:sha1:6c4265a541c9e431961113c1a5d92fb4628bfe13
one-byte NOPs. If the processor actually executes those NOPs, as it sometimes
does with aligned bundling, this can have a performance impact. From my
micro-benchmarks run on my one machine, a 15-byte NOP followed by twelve
one-byte NOPs is about 20% worse than a 15 followed by a 12. This patch
changes NOP emission to emit as many 15-byte (the maximum) as possible followed
by at most one shorter NOP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176464 91177308-0d34-0410-b5e6-96231b3b80d8
Fix typo in X86BaseInfo.h that I introduced in r157818.2013-01-29T14:05:57ZHans Wennborghans@hanshq.net2013-01-29T14:05:57Zurn:sha1:7c1ac767691b2cb5d3367e667e51714f34eb675b
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173798 91177308-0d34-0410-b5e6-96231b3b80d8
Initial patch for x32 ABI support.2013-01-22T18:02:49ZEli Benderskyeliben@google.com2013-01-22T18:02:49Zurn:sha1:9dd2a3b1f2c253e20262535bb89b1ab6cc680ece
Add the x32 environment kind to the triple, and separate the concept of
pointer size and callee save stack slot size, since they're not equal
on x32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173175 91177308-0d34-0410-b5e6-96231b3b80d8
Renamed MCInstFragment to MCRelaxableFragment and added some comments.2013-01-08T00:22:56ZEli Benderskyeliben@google.com2013-01-08T00:22:56Zurn:sha1:251040bc18eedfa56d01fe92836e55cfd8c5d990
No change in functionality.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171822 91177308-0d34-0410-b5e6-96231b3b80d8
MC: Add MCInstrDesc::mayAffectControlFlow() method.2012-12-19T23:38:53ZJim Grosbachgrosbach@apple.com2012-12-19T23:38:53Zurn:sha1:fbf3b4a07690751f72302757058ab0298dfb832e
MC disassembler clients (LLDB) are interested in querying if an
instruction may affect control flow other than by virtue of being
an explicit branch instruction. For example, instructions which
write directly to the PC on some architectures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170610 91177308-0d34-0410-b5e6-96231b3b80d8
Fix a bogus comment2012-12-13T00:24:56ZEli Benderskyeliben@google.com2012-12-13T00:24:56Zurn:sha1:e1d31008c9950ada1a92d0499acb001a2dd76a84
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170052 91177308-0d34-0410-b5e6-96231b3b80d8
Use the new script to sort the includes of every file under lib.2012-12-03T16:50:05ZChandler Carruthchandlerc@gmail.com2012-12-03T16:50:05Zurn:sha1:d04a8d4b33ff316ca4cf961e06c9e312eff8e64f
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.
Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
Add support of RTM from TSX extension2012-11-08T07:28:54ZMichael Liaomichael.liao@intel.com2012-11-08T07:28:54Zurn:sha1:be02a90de17f857ba65bbd8a11653ca1bad30adc
- Add RTM code generation support throught 3 X86 intrinsics:
xbegin()/xend() to start/end a transaction region, and xabort() to abort a
tranaction region
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167573 91177308-0d34-0410-b5e6-96231b3b80d8