<feed xmlns='http://www.w3.org/2005/Atom'>
<title>llvm/lib/Target/Sparc, branch stable</title>
<subtitle>http://llvm.org</subtitle>
<id>https://git.amat.us/llvm/atom/lib/Target/Sparc?h=stable</id>
<link rel='self' href='https://git.amat.us/llvm/atom/lib/Target/Sparc?h=stable'/>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/'/>
<updated>2013-03-24T19:37:04Z</updated>
<entry>
<title>Clean up Sparc patterns.</title>
<updated>2013-03-24T19:37:04Z</updated>
<author>
<name>Jakob Stoklund Olesen</name>
<email>stoklund@2pi.dk</email>
</author>
<published>2013-03-24T19:37:04Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=d28e30fcf44b22c897914343fce9061eb62d3b47'/>
<id>urn:sha1:d28e30fcf44b22c897914343fce9061eb62d3b47</id>
<content type='text'>
The types of register variables no longer need to be specified in output
patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177845 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Give Sparc instruction patterns direct types instead of register classes.</title>
<updated>2013-03-24T00:56:20Z</updated>
<author>
<name>Jakob Stoklund Olesen</name>
<email>stoklund@2pi.dk</email>
</author>
<published>2013-03-24T00:56:20Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=15a3c18623a05a8b9f2f4ea0b0c15965fda4fe6f'/>
<id>urn:sha1:15a3c18623a05a8b9f2f4ea0b0c15965fda4fe6f</id>
<content type='text'>
Also update the documentation since Sparc is the nicest backend, and
used as an example in WritingAnLLVMBackend.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177835 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Use direct types in Sparc def : Pat patterns.</title>
<updated>2013-03-23T20:35:05Z</updated>
<author>
<name>Jakob Stoklund Olesen</name>
<email>stoklund@2pi.dk</email>
</author>
<published>2013-03-23T20:35:05Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=edf03820f1d10bbefcb2821e1e0326cad114ed2e'/>
<id>urn:sha1:edf03820f1d10bbefcb2821e1e0326cad114ed2e</id>
<content type='text'>
The SelectionDAG graph has MVT type labels, not register classes, so
this makes it clearer what is happening.

This notation is also robust against adding more types to the IntRegs
register class.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177829 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Provide the register scavenger to processFunctionBeforeFrameFinalized</title>
<updated>2013-03-14T20:33:40Z</updated>
<author>
<name>Hal Finkel</name>
<email>hfinkel@anl.gov</email>
</author>
<published>2013-03-14T20:33:40Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=3080d23fde4981835d8a7faf46c152441fadb11f'/>
<id>urn:sha1:3080d23fde4981835d8a7faf46c152441fadb11f</id>
<content type='text'>
Add the current PEI register scavenger as a parameter to the
processFunctionBeforeFrameFinalized callback.

This change is necessary in order to allow the PowerPC target code to
set the register scavenger frame index after the save-area offset
adjustments performed by processFunctionBeforeFrameFinalized. Only
after these adjustments have been made is it possible to estimate
the size of the stack frame.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177108 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>ArrayRefize some code. No functionality change.</title>
<updated>2013-03-07T20:33:29Z</updated>
<author>
<name>Benjamin Kramer</name>
<email>benny.kra@googlemail.com</email>
</author>
<published>2013-03-07T20:33:29Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=3853f74aba301ef08b699bac2fa8e53230714a58'/>
<id>urn:sha1:3853f74aba301ef08b699bac2fa8e53230714a58</id>
<content type='text'>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176648 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Move the eliminateCallFramePseudoInstr method from TargetRegisterInfo</title>
<updated>2013-02-21T20:05:00Z</updated>
<author>
<name>Eli Bendersky</name>
<email>eliben@google.com</email>
</author>
<published>2013-02-21T20:05:00Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=700ed80d3da5e98e05ceb90e9bfb66058581a6db'/>
<id>urn:sha1:700ed80d3da5e98e05ceb90e9bfb66058581a6db</id>
<content type='text'>
to TargetFrameLowering, where it belongs. Incidentally, this allows us
to delete some duplicated (and slightly different!) code in TRI.

There are potentially other layering problems that can be cleaned up
as a result, or in a similar manner.

The refactoring was OK'd by Anton Korobeynikov on llvmdev.

Note: this touches the target interfaces, so out-of-tree targets may
be affected.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175788 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Move MRI liveouts to Sparc return instructions.</title>
<updated>2013-02-05T18:16:58Z</updated>
<author>
<name>Jakob Stoklund Olesen</name>
<email>stoklund@2pi.dk</email>
</author>
<published>2013-02-05T18:16:58Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=067e5a2a1a3ed35bce7dc9e9b2eedee501db53c9'/>
<id>urn:sha1:067e5a2a1a3ed35bce7dc9e9b2eedee501db53c9</id>
<content type='text'>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174413 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>[PEI] Pass the frame index operand number to the eliminateFrameIndex function.</title>
<updated>2013-01-31T20:02:54Z</updated>
<author>
<name>Chad Rosier</name>
<email>mcrosier@apple.com</email>
</author>
<published>2013-01-31T20:02:54Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=108fb3202af6f500073cdbb7be32c25d7a273a2e'/>
<id>urn:sha1:108fb3202af6f500073cdbb7be32c25d7a273a2e</id>
<content type='text'>
Each target implementation was needlessly recomputing the index.
Part of rdar://13076458

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174083 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Teach SDISel to combine fsin / fcos into a fsincos node if the following</title>
<updated>2013-01-29T02:32:37Z</updated>
<author>
<name>Evan Cheng</name>
<email>evan.cheng@apple.com</email>
</author>
<published>2013-01-29T02:32:37Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=8688a58c53b46d2dda9bf50dafd5195790a7ed58'/>
<id>urn:sha1:8688a58c53b46d2dda9bf50dafd5195790a7ed58</id>
<content type='text'>
conditions are met:
1. They share the same operand and are in the same BB.
2. Both outputs are used.
3. The target has a native instruction that maps to ISD::FSINCOS node or
   the target provides a sincos library call.

Implemented the generic optimization in sdisel and enabled it for
Mac OSX. Also added an additional optimization for x86_64 Mac OSX by
using an alternative entry point __sincos_stret which returns the two
results in xmm0 / xmm1.

rdar://13087969
PR13204


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173755 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Clean up assignment of CalleeSaveStackSlotSize: get rid of the default and explicitly set this in every target that needs to change it from the default.</title>
<updated>2013-01-23T16:22:04Z</updated>
<author>
<name>Eli Bendersky</name>
<email>eliben@google.com</email>
</author>
<published>2013-01-23T16:22:04Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=e752feee5228bfa33acee35ef9c606ce12f0f173'/>
<id>urn:sha1:e752feee5228bfa33acee35ef9c606ce12f0f173</id>
<content type='text'>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173270 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
</feed>
