llvm/lib/Target/R600, branch testinghttp://llvm.orghttps://git.amat.us/llvm/atom/lib/Target/R600?h=testing2013-03-18T11:34:16ZR600/SI: implement indirect adressing for SI2013-03-18T11:34:16ZChristian Konigchristian.koenig@amd.com2013-03-18T11:34:16Zurn:sha1:b9e8678025891a3eb5431c652df541b632902fc6
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177277 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: add float vector types2013-03-18T11:34:10ZChristian Konigchristian.koenig@amd.com2013-03-18T11:34:10Zurn:sha1:2d7f19e1e971a96186da15dc35ddb52b6163e36e
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177276 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: add shl pattern2013-03-18T11:34:05ZChristian Konigchristian.koenig@amd.com2013-03-18T11:34:05Zurn:sha1:b87082228bb5151598addcf0eb3756cf0f906ab6
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177275 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: add BUFFER_LOAD_DWORD pattern2013-03-18T11:34:00ZChristian Konigchristian.koenig@amd.com2013-03-18T11:34:00Zurn:sha1:2d054cb10eb1e6f2daa1e7a3e9f92e81658e4a3e
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177274 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: implement SI.load.const intrinsic2013-03-18T11:33:55ZChristian Konigchristian.koenig@amd.com2013-03-18T11:33:55Zurn:sha1:b3affde9559061216b821316815b1b273b275f4c
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177273 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: enable all S_LOAD and S_BUFFER_LOAD opcodes2013-03-18T11:33:50ZChristian Konigchristian.koenig@amd.com2013-03-18T11:33:50Zurn:sha1:13e876b27b99826d4a5bb417337b9d2dd712d03f
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177272 91177308-0d34-0410-b5e6-96231b3b80d8
R600/SI: fix inserting waits for all defines2013-03-18T11:33:45ZChristian Konigchristian.koenig@amd.com2013-03-18T11:33:45Zurn:sha1:ae621a2bc99eb3870b90120d1f1552dd96f04bb7
Unfortunately the previous fix for inserting waits for unordered
defines wasn't sufficient, cause it's possible that even ordered
defines are only partially used (or not used at all).
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177271 91177308-0d34-0410-b5e6-96231b3b80d8
R600: Factorize code handling Const Read Port limitation2013-03-14T15:50:45ZVincent Lejeunevljn@ovi.com2013-03-14T15:50:45Zurn:sha1:3ab0ba3cd8a499ebcc7eda3d7585c5ab4e7f0711
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177078 91177308-0d34-0410-b5e6-96231b3b80d8
R600: Remove unused Outputs variable2013-03-13T20:13:25ZVincent Lejeunevljn@ovi.com2013-03-13T20:13:25Zurn:sha1:321aded62349b7369dc999a104944b5304199d83
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176967 91177308-0d34-0410-b5e6-96231b3b80d8
R600: Fix JUMP handling so that MachineInstr verification can occur2013-03-11T18:15:06ZVincent Lejeunevljn@ovi.com2013-03-11T18:15:06Zurn:sha1:fd49dac48fee6da580157515dec55ed2f2d8f2b3
This allows R600 Target to use the newly created -verify-misched llc flag
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176819 91177308-0d34-0410-b5e6-96231b3b80d8