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<title>llvm/lib/Target/PowerPC, branch stable</title>
<subtitle>http://llvm.org</subtitle>
<id>https://git.amat.us/llvm/atom/lib/Target/PowerPC?h=stable</id>
<link rel='self' href='https://git.amat.us/llvm/atom/lib/Target/PowerPC?h=stable'/>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/'/>
<updated>2013-04-01T18:42:58Z</updated>
<entry>
<title>Fix a bad assert in PPCTargetLowering</title>
<updated>2013-04-01T18:42:58Z</updated>
<author>
<name>Hal Finkel</name>
<email>hfinkel@anl.gov</email>
</author>
<published>2013-04-01T18:42:58Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=a1646ceb9a5da080607e503c8bd36241aa465613'/>
<id>urn:sha1:a1646ceb9a5da080607e503c8bd36241aa465613</id>
<content type='text'>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178489 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Add more PPC floating-point conversion instructions</title>
<updated>2013-04-01T17:52:07Z</updated>
<author>
<name>Hal Finkel</name>
<email>hfinkel@anl.gov</email>
</author>
<published>2013-04-01T17:52:07Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=46479197843ecb651adc9417c49bbd1b00acfcb6'/>
<id>urn:sha1:46479197843ecb651adc9417c49bbd1b00acfcb6</id>
<content type='text'>
The P7 and A2 have additional floating-point conversion instructions which
allow a direct two-instruction sequence (plus load/store) to convert from all
combinations (signed/unsigned i32/i64) &lt;--&gt; (float/double) (on previous cores,
only some combinations were directly available).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178480 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Use ImmToIdxMap.count in PPCRegisterInfo</title>
<updated>2013-04-01T17:02:06Z</updated>
<author>
<name>Hal Finkel</name>
<email>hfinkel@anl.gov</email>
</author>
<published>2013-04-01T17:02:06Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=a1f4290ac94f34173e3561c717390de07dccc646'/>
<id>urn:sha1:a1f4290ac94f34173e3561c717390de07dccc646</id>
<content type='text'>
Code improvement suggested by Jakob (in review of r178450). No functionality
change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178473 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Add the PPC popcntw instruction</title>
<updated>2013-04-01T15:58:15Z</updated>
<author>
<name>Hal Finkel</name>
<email>hfinkel@anl.gov</email>
</author>
<published>2013-04-01T15:58:15Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=1fce88313e4d46fdd432b68f7c54fde972c0b526'/>
<id>urn:sha1:1fce88313e4d46fdd432b68f7c54fde972c0b526</id>
<content type='text'>
The popcntw instruction is available whenever the popcntd instruction is
available, and performs a separate popcnt on the lower and upper 32-bits.
Ignoring the high-order count, this can be used for the 32-bit input case
(saving on the explicit zero extension otherwise required to use popcntd).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178470 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Treat PPCISD::STFIWX like the memory opcode that it is</title>
<updated>2013-04-01T15:37:53Z</updated>
<author>
<name>Hal Finkel</name>
<email>hfinkel@anl.gov</email>
</author>
<published>2013-04-01T15:37:53Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=f170cc9b2eb98efee40ee22cff6bcf401c209b00'/>
<id>urn:sha1:f170cc9b2eb98efee40ee22cff6bcf401c209b00</id>
<content type='text'>
PPCISD::STFIWX is really a memory opcode, and so it should come after
FIRST_TARGET_MEMORY_OPCODE, and we should use DAG.getMemIntrinsicNode to create
nodes using it.

No functionality change intended (although there could be optimization benefits
from preserving the MMO information).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178468 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Cleanup ImmToIdxMap and noImmForm in PPCRegisterInfo</title>
<updated>2013-03-31T14:43:31Z</updated>
<author>
<name>Hal Finkel</name>
<email>hfinkel@anl.gov</email>
</author>
<published>2013-03-31T14:43:31Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=4345e8040f14781d20fd5fa2f7ee3c75fa611fa1'/>
<id>urn:sha1:4345e8040f14781d20fd5fa2f7ee3c75fa611fa1</id>
<content type='text'>
ImmToIdxMap should be a DenseMap (not a std::map) because there
is no ordering requirement. Also, we don't need a separate list
of instructions for noImmForm in eliminateFrameIndex, because this
list is essentially the complement of the keys in ImmToIdxMap.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178450 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Add the PPC lfiwax instruction</title>
<updated>2013-03-31T10:12:51Z</updated>
<author>
<name>Hal Finkel</name>
<email>hfinkel@anl.gov</email>
</author>
<published>2013-03-31T10:12:51Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=8049ab15e4b638a07d6f230329945c2310eca27b'/>
<id>urn:sha1:8049ab15e4b638a07d6f230329945c2310eca27b</id>
<content type='text'>
This instruction is available on modern PPC64 CPUs, and is now used
to improve the SINT_TO_FP lowering (by eliminating the need for the
separate sign extension instruction and decreasing the amount of
needed stack space).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178446 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Cleanup PPC(64) i32 -&gt; float/double conversion</title>
<updated>2013-03-31T01:58:02Z</updated>
<author>
<name>Hal Finkel</name>
<email>hfinkel@anl.gov</email>
</author>
<published>2013-03-31T01:58:02Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=9ad0f4907b3ba0916a8b6cdb95d298d2ddb7d405'/>
<id>urn:sha1:9ad0f4907b3ba0916a8b6cdb95d298d2ddb7d405</id>
<content type='text'>
The existing SINT_TO_FP code for i32 -&gt; float/double conversion was disabled
because it relied on broken EXTSW_32/STD_32 instruction definitions. The
original intent had been to enable these 64-bit instructions to be used on CPUs
that support them even in 32-bit mode.  Unfortunately, this form of lying to
the infrastructure was buggy (as explained in the FIXME comment) and had
therefore been disabled.

This re-enables this functionality, using regular DAG nodes, but only when
compiling in 64-bit mode. The old STD_32/EXTSW_32 definitions (which were dead)
are removed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178438 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Implement FRINT lowering on PPC using frin</title>
<updated>2013-03-29T19:41:55Z</updated>
<author>
<name>Hal Finkel</name>
<email>hfinkel@anl.gov</email>
</author>
<published>2013-03-29T19:41:55Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=0882fd6c4f90f1cbaa4bb6f6ceec289428cca734'/>
<id>urn:sha1:0882fd6c4f90f1cbaa4bb6f6ceec289428cca734</id>
<content type='text'>
Like nearbyint, rint can be implemented on PPC using the frin instruction. The
complication comes from the fact that rint needs to set the FE_INEXACT flag
when the result does not equal the input value (and frin does not do that). As
a result, we use a custom inserter which, after the rounding, compares the
rounded value with the original, and if they differ, explicitly sets the XX bit
in the FPSCR register (which corresponds to FE_INEXACT).

Once LLVM has better modeling of the floating-point environment we should be
able to (often) eliminate this extra complexity.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178362 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Remove the old CodePlacementOpt pass.</title>
<updated>2013-03-29T17:14:24Z</updated>
<author>
<name>Benjamin Kramer</name>
<email>benny.kra@googlemail.com</email>
</author>
<published>2013-03-29T17:14:24Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=74a4533a4290b7c6f1fe04a30ca13ec25c529e0a'/>
<id>urn:sha1:74a4533a4290b7c6f1fe04a30ca13ec25c529e0a</id>
<content type='text'>
It was superseded by MachineBlockPlacement and disabled by default since LLVM 3.1.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178349 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
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