llvm/lib/Target/PowerPC, branch release_27http://llvm.orghttps://git.amat.us/llvm/atom/lib/Target/PowerPC?h=release_272010-03-02T06:34:30ZSink InstructionSelect() out of each target into SDISel, and rename it2010-03-02T06:34:30ZChris Lattnersabre@nondot.org2010-03-02T06:34:30Zurn:sha1:7c306da505e2d7f64e160890b274a47fa0740962
DoInstructionSelection. Inline "SelectRoot" into it from DAGISelHeader.
Sink some other stuff out of DAGISelHeader into SDISel.
Eliminate the various 'Indent' stuff from various targets, which dates
to when isel was recursive.
17 files changed, 114 insertions(+), 430 deletions(-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97555 91177308-0d34-0410-b5e6-96231b3b80d8
Remove dead parameter passing.2010-03-02T01:55:18ZBill Wendlingisanbard@gmail.com2010-03-02T01:55:18Zurn:sha1:46ada19645c981a0b7932487d163f7582074a4d9
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97536 91177308-0d34-0410-b5e6-96231b3b80d8
Floating-point add, sub, and mul are now spelled fadd, fsub, and fmul,2010-03-02T01:11:08ZDan Gohmangohman@apple.com2010-03-02T01:11:08Zurn:sha1:a9445e11c553855a6caacbbbf77a9b993ecc651e
respectively.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97531 91177308-0d34-0410-b5e6-96231b3b80d8
remove a bogus pattern, which had the same pattern as STDU2010-02-27T21:15:32ZChris Lattnersabre@nondot.org2010-02-27T21:15:32Zurn:sha1:9fa200d2a2360412465bbd6cfb485af2e9d5b1b4
but codegen'd differently. This really wanted to use some
sort of subreg to get the low 4 bytes of the G8RC register
or something. However, it's invalid and nothing is testing
it, so I'm just zapping the bogosity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97345 91177308-0d34-0410-b5e6-96231b3b80d8
Merge PPC instructions FMRS and FMRD into a single FMR instruction.2010-02-26T21:53:24ZJakob Stoklund Olesenstoklund@2pi.dk2010-02-26T21:53:24Zurn:sha1:baafcbb4dbbda50d5b811b6888c77fd64d073865
This is possible because F8RC is a subclass of F4RC. We keep FMRSD around so
fextend has a pattern.
Also allow folding of memory operands on FMRSD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97275 91177308-0d34-0410-b5e6-96231b3b80d8
Use the right floating point load/store instructions in PPCInstrInfo::foldMemoryOperandImpl().2010-02-26T21:09:24ZJakob Stoklund Olesenstoklund@2pi.dk2010-02-26T21:09:24Zurn:sha1:243296690ec78fc918762bd73896b09e26537f47
The PowerPC floating point registers can represent both f32 and f64 via the
two register classes F4RC and F8RC. F8RC is considered a subclass of F4RC to
allow cross-class coalescing. This coalescing only affects whether registers
are spilled as f32 or f64.
Spill slots must be accessed with load/store instructions corresponding to the
class of the spilled register. PPCInstrInfo::foldMemoryOperandImpl was looking
at the instruction opcode which is wrong.
X86 has similar floating point register classes, but doesn't try to fold
memory operands, so there is no problem there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97262 91177308-0d34-0410-b5e6-96231b3b80d8
remove a bunch of dead named arguments in input patterns,2010-02-23T06:54:29ZChris Lattnersabre@nondot.org2010-02-23T06:54:29Zurn:sha1:6d9f86b7735700f8881e0359fa90c33f984ce2d9
though some look dubious afaict, these are all ok.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96899 91177308-0d34-0410-b5e6-96231b3b80d8
Eliminate some uses of immAllOnes, just use -1, it does2010-02-21T03:12:16ZChris Lattnersabre@nondot.org2010-02-21T03:12:16Zurn:sha1:9f036412ac6f66405f07259185bc63153fb8e059
the same thing and is more efficient for the matcher.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96712 91177308-0d34-0410-b5e6-96231b3b80d8
Really reserve R2 on PPC Darwin. PR 6314.2010-02-16T21:53:27ZDale Johannesendalej@apple.com2010-02-16T21:53:27Zurn:sha1:5994fd0f4d6bbe6955ac07b39e3befb4f5834134
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96399 91177308-0d34-0410-b5e6-96231b3b80d8
Drop support for the InReg attribute on the ppc backend. This was used by2010-02-16T01:50:18ZRafael Espindolarafael.espindola@gmail.com2010-02-16T01:50:18Zurn:sha1:a3b1119977857c7e424f83b25b7e1c7c00783429
llvm-gcc but has been replaced with pad argument which don't need any
special backend support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96312 91177308-0d34-0410-b5e6-96231b3b80d8