<feed xmlns='http://www.w3.org/2005/Atom'>
<title>llvm/lib/Target/PowerPC/InstPrinter, branch release_32</title>
<subtitle>http://llvm.org</subtitle>
<id>https://git.amat.us/llvm/atom/lib/Target/PowerPC/InstPrinter?h=release_32</id>
<link rel='self' href='https://git.amat.us/llvm/atom/lib/Target/PowerPC/InstPrinter?h=release_32'/>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/'/>
<updated>2012-10-08T18:59:53Z</updated>
<entry>
<title>PR12716: PPC crashes on vector compare</title>
<updated>2012-10-08T18:59:53Z</updated>
<author>
<name>Adhemerval Zanella</name>
<email>azanella@linux.vnet.ibm.com</email>
</author>
<published>2012-10-08T18:59:53Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=1c7d69bbe2de22f386ffd9ef4480f8a77be28130'/>
<id>urn:sha1:1c7d69bbe2de22f386ffd9ef4480f8a77be28130</id>
<content type='text'>
Vector compare using altivec 'vcmpxxx' instructions have as third argument
a vector register instead of CR one, different from integer and float-point
compares. This leads to a failure in code generation, where 'SelectSETCC'
expects a DAG with a CR register and gets vector register instead.

This patch changes the behavior by just returning a DAG with the 
vector compare instruction based on the type. The patch also adds a testcase
for all vector types llvm defines.

It also included a fix on signed 5-bits predicates printing, where
signed values were not handled correctly as signed (char are unsigned by
default for PowerPC). This generates 'vspltisw' (vector splat)
instruction with SIM out of range.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165419 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Fix integer undefined behavior due to signed left shift overflow in LLVM.</title>
<updated>2012-08-24T23:29:28Z</updated>
<author>
<name>Richard Smith</name>
<email>richard-llvm@metafoo.co.uk</email>
</author>
<published>2012-08-24T23:29:28Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=1144af3c9b4da48cd581156e05b24261c8de366a'/>
<id>urn:sha1:1144af3c9b4da48cd581156e05b24261c8de366a</id>
<content type='text'>
Reviewed offline by chandlerc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162623 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Silence an unused variable warning on release builds.</title>
<updated>2012-06-23T08:09:30Z</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@gmail.com</email>
</author>
<published>2012-06-23T08:09:30Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=0a2f793d6e24acd00d9209b46436b4899feb1cdb'/>
<id>urn:sha1:0a2f793d6e24acd00d9209b46436b4899feb1cdb</id>
<content type='text'>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159074 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Add support for the PPC isel instruction.</title>
<updated>2012-06-22T23:10:08Z</updated>
<author>
<name>Hal Finkel</name>
<email>hfinkel@anl.gov</email>
</author>
<published>2012-06-22T23:10:08Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=009f7afbeb77d1cc8e962bac7057b73b6d39d62f'/>
<id>urn:sha1:009f7afbeb77d1cc8e962bac7057b73b6d39d62f</id>
<content type='text'>
The isel (integer select) instruction is supported on the 440 and A2
embedded cores and on the POWER7.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159045 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Move getOpcodeName from the various target InstPrinters into the superclass MCInstPrinter.</title>
<updated>2012-04-02T08:32:38Z</updated>
<author>
<name>Benjamin Kramer</name>
<email>benny.kra@googlemail.com</email>
</author>
<published>2012-04-02T08:32:38Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=c97ef618d2d849a272a353c2b4343fc5902cd921'/>
<id>urn:sha1:c97ef618d2d849a272a353c2b4343fc5902cd921</id>
<content type='text'>
All implementations used the same code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153866 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Remove getInstructionName from MCInstPrinter implementations in favor of using the instruction name table from MCInstrInfo. Reduces static data in the InstPrinter implementations.</title>
<updated>2012-04-02T07:01:04Z</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@gmail.com</email>
</author>
<published>2012-04-02T07:01:04Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=7c0b3c1fb6395475e262d66ee403645f0c67dee2'/>
<id>urn:sha1:7c0b3c1fb6395475e262d66ee403645f0c67dee2</id>
<content type='text'>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153863 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Make MCInstrInfo available to the MCInstPrinter. This will be used to remove getInstructionName and the static data it contains since the same tables are already in MCInstrInfo.</title>
<updated>2012-04-02T06:09:36Z</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@gmail.com</email>
</author>
<published>2012-04-02T06:09:36Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=17463b3ef1a3d39b10619254f12e806c8c43f9e7'/>
<id>urn:sha1:17463b3ef1a3d39b10619254f12e806c8c43f9e7</id>
<content type='text'>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153860 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Make MCRegisterInfo available to the the MCInstPrinter.</title>
<updated>2012-03-05T19:33:20Z</updated>
<author>
<name>Jim Grosbach</name>
<email>grosbach@apple.com</email>
</author>
<published>2012-03-05T19:33:20Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=c6449b636f4984be88f128d0375c056ad05e7e8f'/>
<id>urn:sha1:c6449b636f4984be88f128d0375c056ad05e7e8f</id>
<content type='text'>
Used to allow context sensitive printing of super-register or sub-register
references.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152043 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.</title>
<updated>2012-02-18T12:03:15Z</updated>
<author>
<name>Jia Liu</name>
<email>proljc@gmail.com</email>
</author>
<published>2012-02-18T12:03:15Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=31d157ae1ac2cd9c787dc3c1d28e64c682803844'/>
<id>urn:sha1:31d157ae1ac2cd9c787dc3c1d28e64c682803844</id>
<content type='text'>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Convert assert(0) to llvm_unreachable</title>
<updated>2012-02-07T02:50:20Z</updated>
<author>
<name>Craig Topper</name>
<email>craig.topper@gmail.com</email>
</author>
<published>2012-02-07T02:50:20Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=bc2198133a1836598b54b943420748e75d5dea94'/>
<id>urn:sha1:bc2198133a1836598b54b943420748e75d5dea94</id>
<content type='text'>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149961 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
</feed>
