llvm/lib/Target/NVPTX, branch masterhttp://llvm.orghttps://git.amat.us/llvm/atom/lib/Target/NVPTX?h=master2013-05-13T01:16:13ZRemove the MachineMove class.2013-05-13T01:16:13ZRafael Espindolarafael.espindola@gmail.com2013-05-13T01:16:13Zurn:sha1:4a971705bc6030dc2e4338b3cd5cffa2e0f88b7b
It was just a less powerful and more confusing version of
MCCFIInstruction. A side effect is that, since MCCFIInstruction uses
dwarf register numbers, calls to getDwarfRegNum are pushed out, which
should allow further simplifications.
I left the MachineModuleInfo::addFrameMove interface unchanged since
this patch was already fairly big.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181680 91177308-0d34-0410-b5e6-96231b3b80d8
Remove unused argument.2013-05-10T18:16:59ZRafael Espindolarafael.espindola@gmail.com2013-05-10T18:16:59Zurn:sha1:6e53180db120b30f600ac31611a9dd47ef7f4921
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181618 91177308-0d34-0410-b5e6-96231b3b80d8
ArrayRefize getMachineNode(). No functionality change.2013-04-19T22:22:57ZMichael Liaomichael.liao@intel.com2013-04-19T22:22:57Zurn:sha1:2a8bea7a8eba9bfa05dcc7a87e9152a0043841b2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179901 91177308-0d34-0410-b5e6-96231b3b80d8
Add support for subsections to the ELF assembler. Fixes PR8717.2013-04-17T21:18:16ZPeter Collingbournepeter@pcc.me.uk2013-04-17T21:18:16Zurn:sha1:df39be6cb4eb44011db3d3e86f8fe463f81ce127
Differential Revision: http://llvm-reviews.chandlerc.com/D598
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179725 91177308-0d34-0410-b5e6-96231b3b80d8
[NVPTX] Fix a few style issues in NVVMReflect2013-04-02T12:37:11ZJustin Holewinskijholewinski@nvidia.com2013-04-02T12:37:11Zurn:sha1:d4ab1926af982e4334978fd9bf9156c7c087f6f5
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178536 91177308-0d34-0410-b5e6-96231b3b80d8
[NVPTX] Remove support for SM < 2.0. This was never fully supported anyway.2013-03-30T14:29:30ZJustin Holewinskijholewinski@nvidia.com2013-03-30T14:29:30Zurn:sha1:b24fc1c7f7545362fe283730d5532fa7e7375c9e
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178417 91177308-0d34-0410-b5e6-96231b3b80d8
[NVPTX] Add NVVMReflect pass to allow compile-time selection of2013-03-30T14:29:25ZJustin Holewinskijholewinski@nvidia.com2013-03-30T14:29:25Zurn:sha1:21fdcb02716f5eae097abfd2f44e40563e90180a
specific code paths.
This allows us to write code like:
if (__nvvm_reflect("FOO"))
// Do something
else
// Do something else
and compile into a library, then give "FOO" a value at kernel
compile-time so the check becomes a no-op.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178416 91177308-0d34-0410-b5e6-96231b3b80d8
[NVPTX] Run clang-format on all NVPTX sources.2013-03-30T14:29:21ZJustin Holewinskijholewinski@nvidia.com2013-03-30T14:29:21Zurn:sha1:3639ce2575660a0e6938d2e84e8bd9a738fd7051
Hopefully this resolves any outstanding style issues and gives us
an automated way of ensuring we conform to the style guidelines.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178415 91177308-0d34-0410-b5e6-96231b3b80d8
[NVPTX] Fix handling of vector arguments2013-03-24T21:17:47ZJustin Holewinskijholewinski@nvidia.com2013-03-24T21:17:47Zurn:sha1:1ce53cb526d23a3988fb12a5294ab1fcb2eb840f
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177847 91177308-0d34-0410-b5e6-96231b3b80d8
DAGCombiner: Use correct value type for checking legality of BR_CC v32013-03-08T15:36:57ZTom Stellardthomas.stellard@amd.com2013-03-08T15:36:57Zurn:sha1:3ef5383b3537a420c5e2ab3e657c378e5185549d
LegalizeDAG.cpp uses the value of the comparison operands when checking
the legality of BR_CC, so DAGCombiner should do the same.
v2:
- Expand more BR_CC value types for NVPTX
v3:
- Expand correct BR_CC value types for Hexagon, Mips, and XCore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176694 91177308-0d34-0410-b5e6-96231b3b80d8