<feed xmlns='http://www.w3.org/2005/Atom'>
<title>llvm/lib/Target/Mips, branch testing</title>
<subtitle>http://llvm.org</subtitle>
<id>https://git.amat.us/llvm/atom/lib/Target/Mips?h=testing</id>
<link rel='self' href='https://git.amat.us/llvm/atom/lib/Target/Mips?h=testing'/>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/'/>
<updated>2013-03-22T00:29:10Z</updated>
<entry>
<title>Fix the invalid opcode for Mips branch instructions in the assembler</title>
<updated>2013-03-22T00:29:10Z</updated>
<author>
<name>Jack Carter</name>
<email>jack.carter@imgtec.com</email>
</author>
<published>2013-03-22T00:29:10Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=d3107fbc54a5b5156f0aabc8788724f1469eb9df'/>
<id>urn:sha1:d3107fbc54a5b5156f0aabc8788724f1469eb9df</id>
<content type='text'>
For mips a branch an 18-bit signed offset (the 16-bit 
offset field shifted left 2 bits) is added to the 
address of the instruction following the branch 
(not the branch itself), in the branch delay slot, 
to form a PC-relative effective target address. 

Previously, the code generator did not perform the 
shift of the immediate branch offset which resulted 
in wrong instruction opcode. This patch fixes the issue.

Contributor: Vladimir Medic



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177687 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>This patch that enables the Mips assembler to use symbols for offset for instructions</title>
<updated>2013-03-22T00:05:30Z</updated>
<author>
<name>Jack Carter</name>
<email>jack.carter@imgtec.com</email>
</author>
<published>2013-03-22T00:05:30Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=25df6a93f3324bd30f44dcb95fd17aff0a92d438'/>
<id>urn:sha1:25df6a93f3324bd30f44dcb95fd17aff0a92d438</id>
<content type='text'>
This patch uses the generated instruction info tables to 
identify memory/load store instructions.
After successful matching and based on the operand type 
and size, it generates additional instructions to the output.

Contributor: Vladimir Medic



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177685 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>This patch enables the Mips .set directive to define aliases</title>
<updated>2013-03-21T21:44:16Z</updated>
<author>
<name>Jack Carter</name>
<email>jack.carter@imgtec.com</email>
</author>
<published>2013-03-21T21:44:16Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=c91b5e197bb41ccb2f9f78b6176e61c848df9e15'/>
<id>urn:sha1:c91b5e197bb41ccb2f9f78b6176e61c848df9e15</id>
<content type='text'>
The .set directive in the Mips the assembler can be 
used to set the value of a symbol to an expression. 
This changes the symbol's value and type to conform 
to the expression's.

Syntax: .set symbol, expression

This patch implements the parsing of the above syntax 
and enables the parser to use defined symbols when 
parsing operands.

Contributor: Vladimir Medic



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177667 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Silence anonymous type in anonymous union warnings.</title>
<updated>2013-03-15T00:42:55Z</updated>
<author>
<name>Eric Christopher</name>
<email>echristo@gmail.com</email>
</author>
<published>2013-03-15T00:42:55Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=a286fc065a5bc846d73c8407a534a1d3c1d70b59'/>
<id>urn:sha1:a286fc065a5bc846d73c8407a534a1d3c1d70b59</id>
<content type='text'>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177135 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Remove some unused variables to clean the Clang -Werror build</title>
<updated>2013-03-14T23:11:07Z</updated>
<author>
<name>David Blaikie</name>
<email>dblaikie@gmail.com</email>
</author>
<published>2013-03-14T23:11:07Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=cacff672dd532d882727a51e73c96f19fde45828'/>
<id>urn:sha1:cacff672dd532d882727a51e73c96f19fde45828</id>
<content type='text'>
(these were added in r177089)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177129 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>[mips] Set isAllocatable bit of unallocatable register classes to 0.</title>
<updated>2013-03-14T23:09:19Z</updated>
<author>
<name>Akira Hatanaka</name>
<email>ahatanaka@mips.com</email>
</author>
<published>2013-03-14T23:09:19Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=7abc88bc83d2b1a0e576fa5cf92de5017d90a792'/>
<id>urn:sha1:7abc88bc83d2b1a0e576fa5cf92de5017d90a792</id>
<content type='text'>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177128 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Add a new method which enables one to change register classes.</title>
<updated>2013-03-14T22:02:09Z</updated>
<author>
<name>Reed Kotler</name>
<email>rkotler@mips.com</email>
</author>
<published>2013-03-14T22:02:09Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=f8b0a08b6a2e2f4eacdb05eae9a8dd704b692b55'/>
<id>urn:sha1:f8b0a08b6a2e2f4eacdb05eae9a8dd704b692b55</id>
<content type='text'>
See the Mips16ISetLowering.cpp patch to see a use of this.
For now now the extra code in Mips16ISetLowering.cpp is a nop but is
used for test purposes. Mips32 registers are setup and then removed and
then the Mips16 registers are setup. 

Normally you need to add register classes and then call
computeRegisterProperties.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177120 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Provide the register scavenger to processFunctionBeforeFrameFinalized</title>
<updated>2013-03-14T20:33:40Z</updated>
<author>
<name>Hal Finkel</name>
<email>hfinkel@anl.gov</email>
</author>
<published>2013-03-14T20:33:40Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=3080d23fde4981835d8a7faf46c152441fadb11f'/>
<id>urn:sha1:3080d23fde4981835d8a7faf46c152441fadb11f</id>
<content type='text'>
Add the current PEI register scavenger as a parameter to the
processFunctionBeforeFrameFinalized callback.

This change is necessary in order to allow the PowerPC target code to
set the register scavenger frame index after the save-area offset
adjustments performed by processFunctionBeforeFrameFinalized. Only
after these adjustments have been made is it possible to estimate
the size of the stack frame.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177108 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>[mips] Fix filename in comment and delete unnecessary lines of code.</title>
<updated>2013-03-14T19:09:52Z</updated>
<author>
<name>Akira Hatanaka</name>
<email>ahatanaka@mips.com</email>
</author>
<published>2013-03-14T19:09:52Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=042b79625f315da6378d06b5480b15894d6b06b1'/>
<id>urn:sha1:042b79625f315da6378d06b5480b15894d6b06b1</id>
<content type='text'>
No functionality changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177104 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
<entry>
<title>Add back lines which were accidentally deleted in CMakeLists.txt.</title>
<updated>2013-03-14T18:46:46Z</updated>
<author>
<name>Akira Hatanaka</name>
<email>ahatanaka@mips.com</email>
</author>
<published>2013-03-14T18:46:46Z</published>
<link rel='alternate' type='text/html' href='https://git.amat.us/llvm/commit/?id=862146b6077f017faa2b2113768e723891a06494'/>
<id>urn:sha1:862146b6077f017faa2b2113768e723891a06494</id>
<content type='text'>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177096 91177308-0d34-0410-b5e6-96231b3b80d8
</content>
</entry>
</feed>
