llvm/lib/Target/Mips, branch stable http://llvm.org https://git.amat.us/llvm/atom/lib/Target/Mips?h=stable 2013-03-30T02:14:45Z [mips] Add patterns for DSP indexed load instructions. 2013-03-30T02:14:45Z Akira Hatanaka ahatanaka@mips.com 2013-03-30T02:14:45Z urn:sha1:fd2cd0db97d78e10288bdf0fb915296c68294237 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178408 91177308-0d34-0410-b5e6-96231b3b80d8 [mips] Define reg+imm load/store pattern templates. 2013-03-30T02:01:48Z Akira Hatanaka ahatanaka@mips.com 2013-03-30T02:01:48Z urn:sha1:175f0fd99aaa66fd4268d0f3ff73d6b76332c99f git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178407 91177308-0d34-0410-b5e6-96231b3b80d8 [mips] Fix DSP instructions to have explicit accumulator register operands. 2013-03-30T01:58:00Z Akira Hatanaka ahatanaka@mips.com 2013-03-30T01:58:00Z urn:sha1:2c2c33a167c82db9abd9b6173c1cdfdaa40c2071 Check that instruction selection can select multiply-add/sub DSP instructions from a pattern that doesn't have intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178406 91177308-0d34-0410-b5e6-96231b3b80d8 Remove unused variables. 2013-03-30T01:46:28Z Akira Hatanaka ahatanaka@mips.com 2013-03-30T01:46:28Z urn:sha1:7e287bfb58e63c4e1068e49e8e1b714f3b9703bc git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178405 91177308-0d34-0410-b5e6-96231b3b80d8 [mips] Move the code which does dag-combine for multiply-add/sub nodes to 2013-03-30T01:42:24Z Akira Hatanaka ahatanaka@mips.com 2013-03-30T01:42:24Z urn:sha1:d593a77b4cf3b81cd657e351e47cad25ee037ce1 derived class MipsSETargetLowering. We shouldn't be generating madd/msub nodes if target is Mips16, since Mips16 doesn't have support for multipy-add/sub instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178404 91177308-0d34-0410-b5e6-96231b3b80d8 [mips] Fix definitions of multiply, multiply-add/sub and divide instructions. 2013-03-30T01:36:35Z Akira Hatanaka ahatanaka@mips.com 2013-03-30T01:36:35Z urn:sha1:f5926fd844a84adcf1ae4f193146f2877997b82c The new instructions have explicit register output operands and use table-gen patterns instead of C++ code to do instruction selection. Mips16's instructions are unaffected by this change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178403 91177308-0d34-0410-b5e6-96231b3b80d8 [mips] Remove function getFPBranchCodeFromCond. Rename invertFPCondCodeAdd. 2013-03-30T01:16:38Z Akira Hatanaka ahatanaka@mips.com 2013-03-30T01:16:38Z urn:sha1:9cf0724cc3a570fe64146fda7518cef5c740e988 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178396 91177308-0d34-0410-b5e6-96231b3b80d8 Fix indentation. 2013-03-30T01:15:17Z Akira Hatanaka ahatanaka@mips.com 2013-03-30T01:15:17Z urn:sha1:2459afe69791ea04f2a060a2acc7104242844ace git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178395 91177308-0d34-0410-b5e6-96231b3b80d8 [mips] Add mips-specific nodes which will be used to select multiply and divide 2013-03-30T01:14:04Z Akira Hatanaka ahatanaka@mips.com 2013-03-30T01:14:04Z urn:sha1:dd958925b0064981f4894ab5b8f37b02faa0c759 instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178394 91177308-0d34-0410-b5e6-96231b3b80d8 [mips] Implement getRepRegClassFor in MipsSETargetLowering. This function is 2013-03-30T01:12:05Z Akira Hatanaka ahatanaka@mips.com 2013-03-30T01:12:05Z urn:sha1:cbcdcfbda5c60d5ac7a492ef8f90b325b6026bd1 called in several places in ScheduleDAGRRList.cpp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178393 91177308-0d34-0410-b5e6-96231b3b80d8