llvm/lib/Target/Mips, branch release_33http://llvm.orghttps://git.amat.us/llvm/atom/lib/Target/Mips?h=release_332013-05-03T23:17:24ZRemove some uneeded pseudos in the presence of the naked function attribute.2013-05-03T23:17:24ZReed Kotlerrkotler@mips.com2013-05-03T23:17:24Zurn:sha1:2bb955a6931580c9bb0472aa29b3fbbabe263295
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181072 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Split the DSP control register and define one register for each field of2013-05-03T18:37:49ZAkira Hatanakaahatanaka@mips.com2013-05-03T18:37:49Zurn:sha1:a2b2200ff8684ba23c64b24c0128a78f4b6e3c73
its fields.
This removes false dependencies between DSP instructions which access different
fields of the the control register. Implicit register operands are added to
instructions RDDSP and WRDSP after instruction selection, depending on the
value of the mask operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181041 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Handle reading, writing or copying of ccond field of DSP control2013-05-02T23:07:05ZAkira Hatanakaahatanaka@mips.com2013-05-02T23:07:05Zurn:sha1:99ad6ac65e8c97a0d3c9d884285dda01f793b7d1
register.
- Define pseudo instructions which store or load ccond field of the DSP
control register.
- Emit the pseudos in MipsSEInstrInfo::storeRegToStack and loadRegFromStack.
- Expand the pseudos before callee-scan save.
- Emit instructions RDDSP or WRDSP to copy between ccond field and GPRs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180969 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Fix the head Mips16RegisterInfo.cpp comment2013-05-02T18:28:03ZRichard Sandifordrsandifo@linux.vnet.ibm.com2013-05-02T18:28:03Zurn:sha1:e2e80cbdcfc5e69fd59715f9dcde3154cffa8169
...aka a test commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180936 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Rename class and functions. Simplify code.2013-05-01T23:41:31ZAkira Hatanakaahatanaka@mips.com2013-05-01T23:41:31Zurn:sha1:f9a5e7e4e9ca91111b15d97fe7461c9061931ff7
No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180897 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Fix handling of instructions which copy to/from accumulator registers.2013-04-30T23:22:09ZAkira Hatanakaahatanaka@mips.com2013-04-30T23:22:09Zurn:sha1:c147c1b994e1187cb471cdb7ee05f5f875eff4e0
Expand copy instructions between two accumulator registers before callee-saved
scan is done. Handle copies between integer GPR and hi/lo registers in
MipsSEInstrInfo::copyPhysReg. Delete pseudo-copy instructions that are not
needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180827 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Instruction selection patterns for DSP-ASE vector select and compare2013-04-30T22:37:26ZAkira Hatanakaahatanaka@mips.com2013-04-30T22:37:26Zurn:sha1:cd6c57917db22a3913a2cdbadfa79fed3547bdec
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180820 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Simplify code.2013-04-30T21:17:07ZAkira Hatanakaahatanaka@mips.com2013-04-30T21:17:07Zurn:sha1:13ec4812fc733c37bb3329982bc044d186e0bea2
No intended functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180807 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Clear isCommutable bit of instructions which are not commutable.2013-04-30T20:40:39ZAkira Hatanakaahatanaka@mips.com2013-04-30T20:40:39Zurn:sha1:b0caf5ff64962fd9ff2977d7c31d6bb88fb8a8a5
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180801 91177308-0d34-0410-b5e6-96231b3b80d8
Mips assembler: .set reorder support2013-04-25T23:31:35ZJack Carterjack.carter@imgtec.com2013-04-25T23:31:35Zurn:sha1:97265a48895a2cda7f04e47bfe935c4fdd71f8ae
Mips have delayslots for certain instructions
like jumps and branches. These are instructions
that follow the branch or jump and are executed
before the jump or branch is completed.
Early Mips compilers could not cope with delayslots
and left them up to the assembler. The assembler would
fill the delayslots with the appropriate instruction,
usually just a nop to allow correct runtime behavior.
The default behavior for this is set with .set reorder.
To tell the assembler that you don't want it to mess with
the delayslot one used .set noreorder.
For backwards compatibility we need to support
.set reorder and have it be the default behavior in the
assembler.
Our support for it is to insert a NOP directly after an
instruction with a delayslot when in .set reorder mode.
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180584 91177308-0d34-0410-b5e6-96231b3b80d8