llvm/lib/Target/Mips, branch masterhttp://llvm.orghttps://git.amat.us/llvm/atom/lib/Target/Mips?h=master2013-05-14T02:13:45ZRemoved an unnamed namespace and forgot to make two of the functions inside2013-05-14T02:13:45ZReed Kotlerrkotler@mips.com2013-05-14T02:13:45Zurn:sha1:5427aa88d5930655ef9e958446489acc1bf9a160
"static".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181754 91177308-0d34-0410-b5e6-96231b3b80d8
This is the first of three patches which creates stubs used for2013-05-14T02:00:24ZReed Kotlerrkotler@mips.com2013-05-14T02:00:24Zurn:sha1:eafa96485a6c3ce0de4f511ed080a64a7a44f2bb
Mips16/32 floating point interoperability.
When Mips16 code calls external functions that would normally have some
of its parameters or return values passed in floating point registers,
it needs (Mips32) helper functions to do this because while in Mips16 mode
there is no ability to access the floating point registers.
In Pic mode, this is done with a set of predefined functions in libc.
This case is already handled in llvm for Mips16.
In static relocation mode, for efficiency reasons, the compiler generates
stubs that the linker will use if it turns out that the external function
is a Mips32 function. (If it's Mips16, then it does not need the helper
stubs).
These stubs are identically named and the linker knows about these tricks
and will not create multiple copies and will delete them if they are not
needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181753 91177308-0d34-0410-b5e6-96231b3b80d8
Mips assembler: Assembler macro ADDIU $rs,imm2013-05-13T20:26:46ZJack Carterjack.carter@imgtec.com2013-05-13T20:26:46Zurn:sha1:f4a1377322a9234c17b1d324c47248bdb5f62158
This patch adds alias for addiu instruction which enables following syntax:
addiu $rs,imm
The macro is translated as:
addiu $rs,$rs,imm
Contributer: Vladimir Medic
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181729 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Add option -mno-ldc1-sdc1.2013-05-13T18:23:35ZAkira Hatanakaahatanaka@mips.com2013-05-13T18:23:35Zurn:sha1:42f562a1694d24b41f36bbb4d4a086a2a470c625
This option is used when the user wants to avoid emitting double precision FP
loads and stores. Double precision FP loads and stores are expanded to single
precision instructions after register allocation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181718 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Define a helper function which creates an instruction with the same2013-05-13T17:57:42ZAkira Hatanakaahatanaka@mips.com2013-05-13T17:57:42Zurn:sha1:151687cb8c4fc65fefcd8964a0c3d77680e90a5c
operands as the prototype instruction but with a different opcode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181714 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Rename functions. No functionality changes.2013-05-13T17:43:19ZAkira Hatanakaahatanaka@mips.com2013-05-13T17:43:19Zurn:sha1:6daba286836e6fb2351e7ebc248e18a5c80e8a31
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181713 91177308-0d34-0410-b5e6-96231b3b80d8
Remove the MachineMove class.2013-05-13T01:16:13ZRafael Espindolarafael.espindola@gmail.com2013-05-13T01:16:13Zurn:sha1:4a971705bc6030dc2e4338b3cd5cffa2e0f88b7b
It was just a less powerful and more confusing version of
MCCFIInstruction. A side effect is that, since MCCFIInstruction uses
dwarf register numbers, calls to getDwarfRegNum are pushed out, which
should allow further simplifications.
I left the MachineModuleInfo::addFrameMove interface unchanged since
this patch was already fairly big.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181680 91177308-0d34-0410-b5e6-96231b3b80d8
Change getFrameMoves to return a const reference.2013-05-11T02:38:11ZRafael Espindolarafael.espindola@gmail.com2013-05-11T02:38:11Zurn:sha1:d84ccfaf50c7843f31ffc74a8a8e33f779453d6e
To add a frame now there is a dedicated addFrameMove which also takes
care of constructing the move itself.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181657 91177308-0d34-0410-b5e6-96231b3b80d8
Checkin in of first of several patches to finish implementation of2013-05-10T22:25:39ZReed Kotlerrkotler@mips.com2013-05-10T22:25:39Zurn:sha1:46090914b783b632618268f2a5c99aab83732688
mips16/mips32 floating point interoperability.
This patch fixes returns from mips16 functions so that if the function
was in fact called by a mips32 hard float routine, then values
that would have been returned in floating point registers are so returned.
Mips16 mode has no floating point instructions so there is no way to
load values into floating point registers.
This is needed when returning float, double, single complex, double complex
in the Mips ABI.
Helper functions in libc for mips16 are available to do this.
For efficiency purposes, these helper functions have a different calling
convention from normal Mips calls.
Registers v0,v1,a0,a1 are used to pass parameters instead of
a0,a1,a2,a3.
This is because v0,v1,a0,a1 are the natural registers used to return
floating point values in soft float. These values can then be moved
to the appropriate floating point registers with no extra cost.
The only register that is modified is ra in this call.
The helper functions make sure that the return values are in the floating
point registers that they would be in if soft float was not in effect
(which it is for mips16, though the soft float is implemented using a mips32
library that uses hard float).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181641 91177308-0d34-0410-b5e6-96231b3b80d8
Remove unused argument.2013-05-10T18:16:59ZRafael Espindolarafael.espindola@gmail.com2013-05-10T18:16:59Zurn:sha1:6e53180db120b30f600ac31611a9dd47ef7f4921
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181618 91177308-0d34-0410-b5e6-96231b3b80d8