llvm/lib/Target/Mips/InstPrinter, branch release_33 http://llvm.org https://git.amat.us/llvm/atom/lib/Target/Mips/InstPrinter?h=release_33 2013-02-05T08:32:10Z This patch that sets the EmitAlias flag in td files 2013-02-05T08:32:10Z Jack Carter jcarter@mips.com 2013-02-05T08:32:10Z urn:sha1:37ef65b9c1b93c386d13089d9ace6a1cc00e82dc and enables the instruction printer to print aliased instructions. Due to usage of RegisterOperands a change in common code (utils/TableGen/AsmWriterEmitter.cpp) is required to get the correct register value if it is a RegisterOperand. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174358 91177308-0d34-0410-b5e6-96231b3b80d8 This patch tackles the problem of parsing Mips 2013-01-12T01:03:14Z Jack Carter jcarter@mips.com 2013-01-12T01:03:14Z urn:sha1:ec3199f675b17b12fd779df557c6bff25aa4e862 register names in the standalone assembler llvm-mc. Registers such as $A1 can represent either a 32 or 64 bit register based on the instruction using it. In addition, based on the abi, $T0 can represent different 32 bit registers. The problem is resolved by the Mips specific AsmParser td definitions changing to work together. Many cases of RegisterClass parameters are now RegisterOperand. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172284 91177308-0d34-0410-b5e6-96231b3b80d8 [CMake] Remove dependencies to intrinsics_gen I introduced in r169724. 2012-12-11T05:53:54Z NAKAMURA Takumi geek4civic@gmail.com 2012-12-11T05:53:54Z urn:sha1:d181342eee9eed65e5428a33646288345cdbdd7a git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169819 91177308-0d34-0410-b5e6-96231b3b80d8 [CMake] Update dependencies to intrinsics_gen corresponding to r169711. 2012-12-10T05:27:15Z NAKAMURA Takumi geek4civic@gmail.com 2012-12-10T05:27:15Z urn:sha1:60608b924da8b5c6681e9c113dfdfc4a0d95d278 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169724 91177308-0d34-0410-b5e6-96231b3b80d8 [mips] Generate big GOT code. 2012-11-21T20:40:38Z Akira Hatanaka ahatanaka@mips.com 2012-11-21T20:40:38Z urn:sha1:f09a03776dbbc882c9b15eeccb8ec847058fbfa0 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168460 91177308-0d34-0410-b5e6-96231b3b80d8 Add HIGHER and HIGHEST relocations to Mips backend. 2012-07-21T03:09:04Z Akira Hatanaka ahatanaka@mips.com 2012-07-21T03:09:04Z urn:sha1:b22c9289b0dd8255f63038e9bb8229111eb082ae git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160599 91177308-0d34-0410-b5e6-96231b3b80d8 Enclose instruction rdhwr with directives, which are needed when target is 2012-07-05T19:26:38Z Akira Hatanaka ahatanaka@mips.com 2012-07-05T19:26:38Z urn:sha1:a7e4558ec861145032865edcf56400be7558c2f8 mips32 rev1 (the directives are emitted when target is mips32r2 too). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159770 91177308-0d34-0410-b5e6-96231b3b80d8 Fix typos found by http://github.com/lyda/misspell-check 2012-06-02T10:20:22Z Benjamin Kramer benny.kra@googlemail.com 2012-06-02T10:20:22Z urn:sha1:d9b0b025612992a0b724eeca8bdf10b1d7a5c355 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157885 91177308-0d34-0410-b5e6-96231b3b80d8 Move getOpcodeName from the various target InstPrinters into the superclass MCInstPrinter. 2012-04-02T08:32:38Z Benjamin Kramer benny.kra@googlemail.com 2012-04-02T08:32:38Z urn:sha1:c97ef618d2d849a272a353c2b4343fc5902cd921 All implementations used the same code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153866 91177308-0d34-0410-b5e6-96231b3b80d8 Remove getInstructionName from MCInstPrinter implementations in favor of using the instruction name table from MCInstrInfo. Reduces static data in the InstPrinter implementations. 2012-04-02T07:01:04Z Craig Topper craig.topper@gmail.com 2012-04-02T07:01:04Z urn:sha1:7c0b3c1fb6395475e262d66ee403645f0c67dee2 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153863 91177308-0d34-0410-b5e6-96231b3b80d8